sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1024

else if (mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1042

CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1136

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

509

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

534

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

537

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

540

dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

542

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

551

next_mode == LUT_RAM_A ? 1:2);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

602

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

946

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

949

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

951

dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

953

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

961

REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

985

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1212

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1215

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1217

dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1219

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1227

REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1252

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1291

else if (mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1309

CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1407

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

63

s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

769

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

796

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

801

dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

803

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

813

CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

82

s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

864

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

235

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

238

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

241

dpp3_configure_gamcor_lut(dpp_base, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

296

next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

299

REG_UPDATE(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, next_mode == LUT_RAM_A ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

69

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

161

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

252

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

255

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

257

dwb3_configure_ogam_lut(dwbc30, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

259

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

267

REG_UPDATE(DWB_OGAM_CONTROL, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

309

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

427

next_mode == LUT_RAM_A ? 1:2);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

450

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

453

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

456

mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

458

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

469

next_mode == LUT_RAM_A ? 1:2);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1242

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

150

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

364

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

365

else if (current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

368

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

371

mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

373

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

383

MPCC_OGAM_SELECT, next_mode == LUT_RAM_A ? 0:1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

460

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

883

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

886

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

888

mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

890

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

898

REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

916

else if (mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

947

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

980

MPC_RMU_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

113

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

279

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

284

mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

286

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

296

MPCC_MCM_1DLUT_SELECT, next_mode == LUT_RAM_A ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

314

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

731

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

734

next_mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

736

mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

738

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

746

REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

774

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

808

MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

896

else if (mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

931

mode = LUT_RAM_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

113

const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

132

mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

134

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

149

mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

151

if (next_mode == LUT_RAM_A)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

87

mode = LUT_RAM_A;