Symbol: LE_SF
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
33
LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, VCO_LD_VAL_OVRD, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
34
LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, VCO_LD_VAL_OVRD_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
35
LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, REF_LD_VAL_OVRD, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
36
LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, REF_LD_VAL_OVRD_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
37
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
38
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
39
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DP4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
40
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_PSTATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
41
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_PSTATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
42
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_MPLL_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
43
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_MPLL_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
44
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
45
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
46
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
47
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
48
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_EN, mask_sh)
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
38
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
39
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_MPLLB_CP_PROP_GS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
40
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_RX_VREF_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
41
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_CP_INT_GS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
42
LE_SF(RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCS_DMCU_DPALT_DIS_BLOCK_REG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
43
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_SUP_PRE_HP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
44
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_DP_TX0_VREGDRV_BYP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
45
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_DP_TX1_VREGDRV_BYP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
46
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_DP_TX2_VREGDRV_BYP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
47
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_DP_TX3_VREGDRV_BYP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
48
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
49
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
50
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
51
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
52
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
53
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
54
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
55
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
56
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
57
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
58
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
59
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
60
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
61
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
62
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
63
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
64
LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
65
LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
66
LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
67
LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
68
LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh)
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
77
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
78
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
79
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
80
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
178
LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
179
LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
180
LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
181
LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
182
LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
183
LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
184
LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
185
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
186
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
187
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
188
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
189
LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
190
LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
191
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
192
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
193
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
194
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
195
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
196
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
197
LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
198
LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
199
LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
200
LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
201
LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
202
LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
203
LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
204
LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
205
LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
206
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
207
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
208
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
209
LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
210
LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
211
LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
212
LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
213
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
214
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
215
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
216
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
217
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
218
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
219
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
220
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
221
LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
222
LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
223
LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
224
LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
225
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
226
LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
100
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
101
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
102
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
103
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
104
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
105
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
106
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
107
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
108
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
109
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
110
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
111
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
112
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
113
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
114
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
115
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
116
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
117
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
118
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
119
LE_SF(RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA, RDPCS_PLL_UPDATE_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
120
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
121
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
122
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
123
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
124
LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
125
LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
126
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
127
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
128
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
129
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
130
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
131
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
132
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
133
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
134
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
135
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
136
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
137
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
138
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
139
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
140
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
141
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
142
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
143
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
144
LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
145
LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
146
LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
147
LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
148
LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
149
LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
150
LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
151
LE_SF(DPCSTX0_DPCSTX_DEBUG_CONFIG, DPCS_DBG_CBUS_DIS, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
155
LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_REF_LD_VAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
156
LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_VCO_LD_VAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
157
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
158
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_PSTATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
159
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_PSTATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
160
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_MPLL_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
161
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_MPLL_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
162
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
163
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
164
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
165
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
166
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
167
LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
168
LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
169
LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
170
LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
171
LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
172
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
173
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
177
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
178
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
179
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
180
LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
181
LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE1EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
182
LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE2EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
183
LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE3EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
184
LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
185
LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
187
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
188
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
189
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
190
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
191
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
192
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
193
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
194
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
195
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
196
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
197
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
198
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
199
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
200
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
36
LE_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
37
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
38
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
39
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
40
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
41
LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
44
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
45
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
46
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
47
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
48
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
49
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
50
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
51
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
52
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
53
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
54
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
55
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
56
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
57
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
58
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
59
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
60
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
61
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
62
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
63
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
64
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
65
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
66
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
67
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
68
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
69
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
70
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
71
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
72
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
73
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
74
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
75
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
76
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
77
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
78
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
79
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
80
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
81
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
82
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
83
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
84
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
85
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
86
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
87
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
88
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
89
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
90
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
91
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
92
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
93
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
94
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
95
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
96
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
97
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
98
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
99
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h
59
LE_SF(DIG0_TMDS_DCBALANCER_CONTROL, TMDS_SYNC_DCBAL_EN, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h
63
LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h
64
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h
65
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h
66
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h
67
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h
60
LE_SF(DIG0_TMDS_DCBALANCER_CONTROL, TMDS_SYNC_DCBAL_EN, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h
64
LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_HDMI_FRL_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h
65
LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP_10_BIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h
66
LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h
67
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h
68
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
100
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
101
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
102
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
103
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
104
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
105
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
106
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
107
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
108
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
109
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
110
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
111
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
112
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
113
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
114
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
115
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
116
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
117
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
118
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
119
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
120
LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
121
LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
122
LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
123
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
124
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
125
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
126
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
127
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
128
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
129
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
130
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
131
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
132
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
133
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
134
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
135
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
136
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
137
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
138
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
139
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
140
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
141
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
142
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
143
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
144
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
145
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
146
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
147
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
148
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
149
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
150
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
151
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
152
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
153
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
154
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
155
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
156
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
157
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
158
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
159
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
160
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
161
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
162
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
163
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
164
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
165
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
166
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
167
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
168
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
169
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
170
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
171
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
172
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
173
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
174
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
175
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
176
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
177
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
178
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
179
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
180
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
181
LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
182
LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
183
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
184
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
185
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
186
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
187
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
188
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
189
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
190
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
191
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
192
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
193
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
194
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
195
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
196
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
197
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
198
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
199
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
200
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
44
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
45
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
46
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
47
LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
48
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
49
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
50
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
51
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
52
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
53
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
54
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
55
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
56
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
57
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
58
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
59
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
60
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
61
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
62
LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
63
LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
64
LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
98
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
99
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
100
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
101
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
102
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
103
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
104
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
105
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
106
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
107
LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
108
LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
109
LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
110
LE_SF(DIO_CLK_CNTL, DISPCLK_R_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
111
LE_SF(DIO_CLK_CNTL, DISPCLK_G_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
112
LE_SF(DIO_CLK_CNTL, REFCLK_R_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
113
LE_SF(DIO_CLK_CNTL, REFCLK_G_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
114
LE_SF(DIO_CLK_CNTL, SOCCLK_G_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
115
LE_SF(DIO_CLK_CNTL, SYMCLK_FE_R_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
116
LE_SF(DIO_CLK_CNTL, SYMCLK_FE_G_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
117
LE_SF(DIO_CLK_CNTL, SYMCLK_R_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
118
LE_SF(DIO_CLK_CNTL, SYMCLK_G_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
119
LE_SF(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
120
LE_SF(DIO_CLK_CNTL, DISPCLK_G_HDCP_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
121
LE_SF(DIO_CLK_CNTL, SYMCLKA_G_HDCP_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
122
LE_SF(DIO_CLK_CNTL, SYMCLKB_G_HDCP_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
123
LE_SF(DIO_CLK_CNTL, SYMCLKC_G_HDCP_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
124
LE_SF(DIO_CLK_CNTL, SYMCLKD_G_HDCP_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
125
LE_SF(DIO_CLK_CNTL, SYMCLKE_G_HDCP_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
126
LE_SF(DIO_CLK_CNTL, SYMCLKF_G_HDCP_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
127
LE_SF(DIO_CLK_CNTL, SYMCLKG_G_HDCP_GATE_DIS, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
33
LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_BE_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
34
LE_SF(DIG0_DIG_BE_CNTL, DIG_RB_SWITCH_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
35
LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
36
LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
37
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
38
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
39
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
40
LE_SF(DIG0_DIG_BE_CLK_CNTL, HDCP_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
41
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
42
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_HDCP_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
43
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_TMDS_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
44
LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
45
LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
46
LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
47
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
48
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
49
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
50
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
51
LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
52
LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
53
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
54
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
55
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
56
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
57
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
58
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
59
LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
60
LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
61
LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
62
LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
63
LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
64
LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
65
LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
66
LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
67
LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
68
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
69
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
70
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
71
LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
72
LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
73
LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
74
LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
75
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
76
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
77
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
78
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
79
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
80
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
81
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
82
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
83
LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
84
LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
85
LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
86
LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
87
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
88
LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
89
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
90
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
91
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
92
LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
93
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
94
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
95
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
96
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
97
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
98
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
99
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
100
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
101
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
102
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
103
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
104
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
105
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
32
LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_BE_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
33
LE_SF(DIG0_DIG_BE_CNTL, DIG_RB_SWITCH_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
34
LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
35
LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
36
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
37
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
38
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
39
LE_SF(DIG0_DIG_BE_CLK_CNTL, HDCP_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
40
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
41
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_HDCP_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
42
LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_TMDS_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
43
LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
44
LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
45
LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
46
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
47
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
48
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
49
LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
50
LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
51
LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
52
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
53
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
54
LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
55
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
56
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
57
LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
58
LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
59
LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
60
LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
61
LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
62
LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
63
LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
64
LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
65
LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
66
LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
67
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
68
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
69
LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
70
LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
71
LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
72
LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
73
LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
74
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
75
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
76
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
77
LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
78
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
79
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
80
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
81
LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
82
LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
83
LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
84
LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
85
LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
86
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
87
LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
88
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
89
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
90
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
91
LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
92
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
93
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
94
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
95
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
96
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
97
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
98
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
99
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \