sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3020

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3026

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3049

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3055

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/pci/drm/radeon/cik.c

6881

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6882

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6884

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6885

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6888

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6889

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

7233

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);

sys/dev/pci/drm/radeon/cik.c

7234

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);

sys/dev/pci/drm/radeon/cik.c

7236

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);

sys/dev/pci/drm/radeon/cik.c

7237

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);

sys/dev/pci/drm/radeon/cik.c

7240

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);

sys/dev/pci/drm/radeon/cik.c

7241

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);