sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

294

case LANE_COUNT_ONE:

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3466

case LANE_COUNT_ONE:

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

428

case LANE_COUNT_ONE:

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

604

DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

618

DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

492

DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

73

NUM_LANES, num_lanes == LANE_COUNT_ONE ? 0 : num_lanes == LANE_COUNT_TWO ? 1 : 3);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

102

.lane_count = LANE_COUNT_ONE,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

473

return lane_count <= LANE_COUNT_ONE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

487

return LANE_COUNT_ONE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

488

case LANE_COUNT_ONE:

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

533

case LANE_COUNT_ONE:

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

670

cur->lane_count = LANE_COUNT_ONE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

723

LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

779

initial_link_setting.lane_count = LANE_COUNT_ONE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

833

initial_link_setting.lane_count = LANE_COUNT_ONE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

84

{LANE_COUNT_ONE, LINK_RATE_UHBR20},

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

87

{LANE_COUNT_ONE, LINK_RATE_UHBR13_5},

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

888

initial_link_setting.lane_count = LANE_COUNT_ONE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

89

{LANE_COUNT_ONE, LINK_RATE_UHBR10},

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

92

{LANE_COUNT_ONE, LINK_RATE_HIGH3},

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

94

{LANE_COUNT_ONE, LINK_RATE_HIGH2},

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

97

{LANE_COUNT_ONE, LINK_RATE_HIGH},

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

98

{LANE_COUNT_ONE, LINK_RATE_LOW},

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1639

(cur_link_settings.lane_count <= LANE_COUNT_ONE);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1781

(cur_link_settings.lane_count <= LANE_COUNT_ONE);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1803

(cur_link_settings.lane_count <= LANE_COUNT_ONE));

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

446

if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)