Symbol: L3_PWM_TIMER_INIT_VAL_MASK
sys/dev/pci/drm/i915/gt/intel_workarounds.c
707
wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
708
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));