Symbol: JH7110_PLL0_FBDIV_OFF
sys/arch/riscv64/dev/stfclock.c
679
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF);
sys/arch/riscv64/dev/stfclock.c
772
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF);
sys/arch/riscv64/dev/stfclock.c
775
regmap_write_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF, reg);