IXGB_WRITE_REG
IXGB_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr);
IXGB_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32));
IXGB_WRITE_REG(&sc->hw, TDLEN,
IXGB_WRITE_REG(&sc->hw, TDH, 0);
IXGB_WRITE_REG(&sc->hw, TDT, 0);
IXGB_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay);
IXGB_WRITE_REG(&sc->hw, TCTL, reg_tctl);
IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl & ~IXGB_RCTL_RXEN);
IXGB_WRITE_REG(&sc->hw, RDTR,
IXGB_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr);
IXGB_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32));
IXGB_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc *
IXGB_WRITE_REG(&sc->hw, RDH, 0);
IXGB_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1);
IXGB_WRITE_REG(&sc->hw, RXDCTL, reg_rxdctl);
IXGB_WRITE_REG(&sc->hw, RAIDC, raidc);
IXGB_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum);
IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
IXGB_WRITE_REG(&sc->hw, RDT, next_to_use);
IXGB_WRITE_REG(&sc->hw, CTRL0, ctrl);
IXGB_WRITE_REG(&sc->hw, IMS, val);
IXGB_WRITE_REG(&sc->hw, IMC, ~0);
IXGB_WRITE_REG(&sc->hw, TDT, sc->next_avail_tx_desc);
IXGB_WRITE_REG(&sc->hw, MFRMS,
IXGB_WRITE_REG(&sc->hw, CTRL0, temp_reg);
IXGB_WRITE_REG(&sc->hw, IMC, IXGB_INT_RXDMT0);
IXGB_WRITE_REG(&sc->hw, IMS, IXGB_INT_RXDMT0);
IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, eecd_reg);
IXGB_WRITE_REG(hw, EECD, *eecd_reg);
IXGB_WRITE_REG(hw, EECD, *eecd_reg);
IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
IXGB_WRITE_REG(hw, CTRL0,
IXGB_WRITE_REG(hw, CTRL0, ctrl);
IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
IXGB_WRITE_REG(hw, IMC, 0xffffffff);
IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
IXGB_WRITE_REG(hw, PAP, pap_reg);
IXGB_WRITE_REG(hw, FCRTL, 0);
IXGB_WRITE_REG(hw, FCRTH, 0);
IXGB_WRITE_REG(hw, FCRTL,
IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
IXGB_WRITE_REG(hw, MSCA, command);
IXGB_WRITE_REG(hw, MSCA, command);
IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
IXGB_WRITE_REG(hw, MSCA, command);
IXGB_WRITE_REG(hw, MSCA, command);
IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);