sys/dev/ic/ar5210.c

1030

AR5K_REG_SM(frame_type, AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE);

sys/dev/ic/ar5210.c

1032

AR5K_REG_SM(tx_rate0, AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE);

sys/dev/ic/ar5210.c

1052

AR5K_REG_SM(key_index,

sys/dev/ic/ar5210.c

2132

AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,

sys/dev/ic/ar5210.c

2134

AR5K_REG_SM(state->bs_interval, AR5K_AR5210_BEACON_PERIOD));

sys/dev/ic/ar5210.c

575

AR5K_REG_SM(-1, AR5K_AR5210_PHY_SIG_FIRPWR));

sys/dev/ic/ar5210.c

580

AR5K_REG_SM(-1, AR5K_AR5210_PHY_AGCCOARSE_HI) |

sys/dev/ic/ar5210.c

581

AR5K_REG_SM(-127, AR5K_AR5210_PHY_AGCCOARSE_LO));

sys/dev/ic/ar5210.c

586

AR5K_REG_SM(2, AR5K_AR5210_PHY_ADCSAT_ICNT) |

sys/dev/ic/ar5210.c

587

AR5K_REG_SM(12, AR5K_AR5210_PHY_ADCSAT_THR));

sys/dev/ic/ar5210.c

856

| AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_AR5210_RETRY_LMT_SLG_RETRY)

sys/dev/ic/ar5210.c

857

| AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_AR5210_RETRY_LMT_SSH_RETRY)

sys/dev/ic/ar5210.c

858

| AR5K_REG_SM(retry_lg, AR5K_AR5210_RETRY_LMT_LG_RETRY)

sys/dev/ic/ar5210.c

859

| AR5K_REG_SM(retry_sh, AR5K_AR5210_RETRY_LMT_SH_RETRY));

sys/dev/ic/ar5211.c

1042

AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) |

sys/dev/ic/ar5211.c

1043

AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC));

sys/dev/ic/ar5211.c

1045

AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR));

sys/dev/ic/ar5211.c

1047

AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN));

sys/dev/ic/ar5211.c

1147

AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) |

sys/dev/ic/ar5211.c

1148

AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT);

sys/dev/ic/ar5211.c

1150

AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE);

sys/dev/ic/ar5211.c

1172

AR5K_REG_SM(key_index,

sys/dev/ic/ar5211.c

2237

AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,

sys/dev/ic/ar5211.c

2238

AR5K_AR5211_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,

sys/dev/ic/ar5211.c

919

AR5K_REG_SM(AR5K_INIT_SLG_RETRY,

sys/dev/ic/ar5211.c

921

AR5K_REG_SM(AR5K_INIT_SSH_RETRY,

sys/dev/ic/ar5211.c

923

AR5K_REG_SM(retry_lg, AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY) |

sys/dev/ic/ar5211.c

924

AR5K_REG_SM(retry_sh, AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY));

sys/dev/ic/ar5211.c

941

AR5K_REG_SM(cw_min, AR5K_AR5211_DCU_LCL_IFS_CW_MIN) |

sys/dev/ic/ar5211.c

942

AR5K_REG_SM(cw_max, AR5K_AR5211_DCU_LCL_IFS_CW_MAX) |

sys/dev/ic/ar5211.c

943

AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,

sys/dev/ic/ar5211.c

954

AR5K_REG_SM(tq->tqi_cbr_period,

sys/dev/ic/ar5211.c

956

AR5K_REG_SM(tq->tqi_cbr_overflow_limit,

sys/dev/ic/ar5211.c

967

AR5K_REG_SM(tq->tqi_ready_time,

sys/dev/ic/ar5211.c

974

AR5K_REG_SM(tq->tqi_burst_time,

sys/dev/ic/ar5212.c

1107

AR5K_REG_SM(AR5K_INIT_SLG_RETRY,

sys/dev/ic/ar5212.c

1109

AR5K_REG_SM(AR5K_INIT_SSH_RETRY,

sys/dev/ic/ar5212.c

1111

AR5K_REG_SM(retry_lg, AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY) |

sys/dev/ic/ar5212.c

1112

AR5K_REG_SM(retry_sh, AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY));

sys/dev/ic/ar5212.c

1129

AR5K_REG_SM(cw_min, AR5K_AR5212_DCU_LCL_IFS_CW_MIN) |

sys/dev/ic/ar5212.c

1130

AR5K_REG_SM(cw_max, AR5K_AR5212_DCU_LCL_IFS_CW_MAX) |

sys/dev/ic/ar5212.c

1131

AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,

sys/dev/ic/ar5212.c

1142

AR5K_REG_SM(tq->tqi_cbr_period,

sys/dev/ic/ar5212.c

1144

AR5K_REG_SM(tq->tqi_cbr_overflow_limit,

sys/dev/ic/ar5212.c

1155

AR5K_REG_SM(tq->tqi_ready_time,

sys/dev/ic/ar5212.c

1162

AR5K_REG_SM(tq->tqi_burst_time,

sys/dev/ic/ar5212.c

1230

AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXOK) |

sys/dev/ic/ar5212.c

1231

AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXDESC));

sys/dev/ic/ar5212.c

1233

AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR1_QCU_TXERR));

sys/dev/ic/ar5212.c

1235

AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN));

sys/dev/ic/ar5212.c

1335

AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) |

sys/dev/ic/ar5212.c

1336

AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT);

sys/dev/ic/ar5212.c

1338

AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE);

sys/dev/ic/ar5212.c

1340

AR5K_REG_SM(tx_tries0, AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0);

sys/dev/ic/ar5212.c

1365

AR5K_REG_SM(key_index,

sys/dev/ic/ar5212.c

1379

AR5K_REG_SM(rtscts_rate,

sys/dev/ic/ar5212.c

1429

AR5K_REG_SM(tx_tries##_n, \

sys/dev/ic/ar5212.c

1432

AR5K_REG_SM(tx_rate##_n, \

sys/dev/ic/ar5212.c

2629

AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,

sys/dev/ic/ar5212.c

2630

AR5K_AR5212_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,

sys/dev/ic/ar5212.c

2663

AR5K_REG_SM((state->bs_nextdtim - 3) << 3,

sys/dev/ic/ar5212.c

2665

AR5K_REG_SM(10, AR5K_AR5212_SLEEP0_CABTO) |

sys/dev/ic/ar5212.c

2669

AR5K_REG_SM((next_beacon - 3) << 3,

sys/dev/ic/ar5212.c

2671

AR5K_REG_SM(10, AR5K_AR5212_SLEEP1_BEACON_TO));

sys/dev/ic/ar5212.c

2673

AR5K_REG_SM(interval, AR5K_AR5212_SLEEP2_TIM_PER) |

sys/dev/ic/ar5212.c

2674

AR5K_REG_SM(dtim, AR5K_AR5212_SLEEP2_DTIM_PER));

sys/dev/ic/ar5212.c

930

AR5K_REG_SM(hal->ah_txpower.txp_max,