AR5K_REG_READ
return (AR5K_REG_READ(AR5K_AR5210_RXDP));
i > 0 && (AR5K_REG_READ(AR5K_AR5210_CR) & AR5K_AR5210_CR_RXE) != 0;
return (AR5K_REG_READ(AR5K_AR5210_RX_FILTER));
printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5210_##_x));
led = AR5K_REG_READ(AR5K_AR5210_PCICFG);
(AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio))
(AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio))
return (((AR5K_REG_READ(AR5K_AR5210_GPIODI) &
data = AR5K_REG_READ(AR5K_AR5210_GPIODO);
data = (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &
return (AR5K_REG_READ(AR5K_AR5210_TSF_L32));
u_int64_t tsf = AR5K_REG_READ(AR5K_AR5210_TSF_U32);
return (AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32));
statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5210_ACK_FAIL);
statistics->rts_bad += AR5K_REG_READ(AR5K_AR5210_RTS_FAIL);
statistics->rts_good += AR5K_REG_READ(AR5K_AR5210_RTS_OK);
statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5210_FCS_FAIL);
statistics->beacons += AR5K_REG_READ(AR5K_AR5210_BEACON_CNT);
return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5210_SLOT_TIME) & 0xffff));
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT),
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT),
if (AR5K_REG_READ(AR5K_AR5210_KEYTABLE_MAC1(entry)) &
staid = AR5K_REG_READ(AR5K_AR5210_STA_ID1);
if ((AR5K_REG_READ(AR5K_AR5210_PCICFG) &
srev = AR5K_REG_READ(AR5K_AR5210_SREV);
hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5210_PHY_CHIP_ID) &
(AR5K_REG_READ(AR5K_AR5210_BEACON) &~
(AR5K_REG_READ(AR5K_AR5210_BSR) &
(AR5K_REG_READ(AR5K_AR5210_CR) &
return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
if ((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == HAL_INT_NOCARD) {
(ar5k_bitswap((AR5K_REG_READ(AR5K_AR5210_PHY(256) >> 28) & 0xf), 4)
return (AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ?
(void)AR5K_REG_READ(AR5K_AR5210_EEPROM_BASE + (4 * offset));
status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS);
(AR5K_REG_READ(AR5K_AR5210_EEPROM_RDATA) & 0xffff);
status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS);
AR5K_REG_READ(ar5210_ini[i].ini_register);
beacon = AR5K_REG_READ(AR5K_AR5210_BEACON);
phy_sig = AR5K_REG_READ(AR5K_AR5210_PHY_SIG);
phy_agc = AR5K_REG_READ(AR5K_AR5210_PHY_AGCCOARSE);
phy_sat = AR5K_REG_READ(AR5K_AR5210_PHY_ADCSAT);
noise_floor = AR5K_REG_READ(AR5K_AR5210_PHY_NF);
trigger_level = AR5K_REG_READ(AR5K_AR5210_TRIG_LVL);
return (AR5K_REG_READ(tx_reg));
tx_queue = AR5K_REG_READ(AR5K_AR5210_CR);
tx_queue = AR5K_REG_READ(AR5K_AR5210_CR);
(AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x1C }, \
return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue)));
pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) &
return (AR5K_REG_READ(AR5K_AR5211_RXDP));
i > 0 && (AR5K_REG_READ(AR5K_AR5211_CR) & AR5K_AR5211_CR_RXE) != 0;
return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER));
printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x));
(AR5K_REG_READ(AR5K_AR5211_BEACON) &
(AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio))
(AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio))
return (((AR5K_REG_READ(AR5K_AR5211_GPIODI) &
data = AR5K_REG_READ(AR5K_AR5211_GPIODO);
data = (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &
return (AR5K_REG_READ(AR5K_AR5211_TSF_L32));
u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32);
return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32));
statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL);
statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL);
statistics->rts_good += AR5K_REG_READ(AR5K_AR5211_RTS_OK);
statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5211_FCS_FAIL);
statistics->beacons += AR5K_REG_READ(AR5K_AR5211_BEACON_CNT);
return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff);
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT),
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT),
if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) &
staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1);
if ((AR5K_REG_READ(AR5K_AR5211_PCICFG) &
srev = AR5K_REG_READ(AR5K_AR5211_SREV);
hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) &
(AR5K_REG_READ(AR5K_AR5211_BEACON) &~
return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
data = AR5K_REG_READ(AR5K_AR5211_RAC_PISR);
AR5K_REG_READ(AR5K_AR5211_RXDP);
return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ?
status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS);
(AR5K_REG_READ(AR5K_AR5211_EEPROM_DATA) & 0xffff);
status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS);
srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff;
s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0));
s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA);
s_led[0] = AR5K_REG_READ(AR5K_AR5211_PCICFG) &
s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR);
s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO);
data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) &
return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA);
AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN)
iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR);
i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I);
q_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_Q);
trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG),
return (AR5K_REG_READ(AR5K_AR5212_QCU_TXDP(queue)));
pending = AR5K_REG_READ(AR5K_AR5212_QCU_STS(queue)) &
return (AR5K_REG_READ(AR5K_AR5212_RXDP));
i > 0 && (AR5K_REG_READ(AR5K_AR5212_CR) & AR5K_AR5212_CR_RXE) != 0;
filter = AR5K_REG_READ(AR5K_AR5212_RX_FILTER);
data = AR5K_REG_READ(AR5K_AR5212_PHY_ERR_FIL);
printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5212_##_x));
(AR5K_REG_READ(AR5K_AR5212_BEACON) &
(AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio))
(AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio))
return (((AR5K_REG_READ(AR5K_AR5212_GPIODI) &
data = AR5K_REG_READ(AR5K_AR5212_GPIODO);
data = (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &
return (AR5K_REG_READ(AR5K_AR5212_TSF_L32));
u_int64_t tsf = AR5K_REG_READ(AR5K_AR5212_TSF_U32);
return (AR5K_REG_READ(AR5K_AR5212_TSF_L32) | (tsf << 32));
statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5212_ACK_FAIL);
statistics->rts_bad += AR5K_REG_READ(AR5K_AR5212_RTS_FAIL);
statistics->rts_good += AR5K_REG_READ(AR5K_AR5212_RTS_OK);
statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5212_FCS_FAIL);
statistics->beacons += AR5K_REG_READ(AR5K_AR5212_BEACON_CNT);
srev = AR5K_REG_READ(AR5K_AR5212_SREV);
data = AR5K_REG_READ(AR5K_AR5212_PHY_PAPD_PROBE);
hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5212_PHY_CHIP_ID) &
return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) & 0xffff);
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT),
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT),
if (AR5K_REG_READ(AR5K_AR5212_KEYTABLE_MAC1(entry)) &
staid = AR5K_REG_READ(AR5K_AR5212_STA_ID1);
if ((AR5K_REG_READ(AR5K_AR5212_PCICFG) &
(AR5K_REG_READ(AR5K_AR5212_BEACON) &~
return (AR5K_REG_READ(AR5K_AR5212_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
data = AR5K_REG_READ(AR5K_AR5212_RAC_PISR);
AR5K_REG_READ(AR5K_AR5212_RXDP);
return (AR5K_REG_READ(AR5K_AR5212_CFG) & AR5K_AR5212_CFG_EEBS ?
status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS);
(AR5K_REG_READ(AR5K_AR5212_EEPROM_DATA) & 0xffff);
status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS);
srev = (AR5K_REG_READ(AR5K_AR5212_PHY(0x100)) >> 24) & 0xff;
s_seq = AR5K_REG_READ(AR5K_AR5212_DCU_SEQNUM(0));
s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA);
s_led[0] = AR5K_REG_READ(AR5K_AR5212_PCICFG) &
s_led[1] = AR5K_REG_READ(AR5K_AR5212_GPIOCR);
s_led[2] = AR5K_REG_READ(AR5K_AR5212_GPIODO);
data = AR5K_REG_READ(AR5K_AR5212_PHY_RX_DELAY) &
return AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA);
AR5K_REG_READ(AR5K_AR5212_PHY_IQ) & AR5K_AR5212_PHY_IQ_RUN)
iq_corr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_CORR);
i_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_I);
q_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_Q);
trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TXCFG),
AR5K_REG_READ((u_int32_t)ini[i].ini_register);
data = AR5K_REG_READ(reg);
AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \
AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags))
AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags))
AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags))
AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
(AR5K_REG_READ(_reg) & (1 << _queue)) \