sys/dev/pci/if_iwnreg.h

117

#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)

sys/dev/pci/if_iwnreg.h

118

#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)

sys/dev/pci/if_iwnreg.h

119

#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)

sys/dev/pci/if_iwnreg.h

120

#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)

sys/dev/pci/if_iwnreg.h

121

#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)

sys/dev/pci/if_iwnreg.h

122

#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)

sys/dev/pci/if_iwnreg.h

123

#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)

sys/dev/pci/if_iwnreg.h

124

#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)

sys/dev/pci/if_iwnreg.h

125

#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)

sys/dev/pci/if_iwnreg.h

126

#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)

sys/dev/pci/if_iwnreg.h

127

#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)

sys/dev/pci/if_iwnreg.h

128

#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)

sys/dev/pci/if_iwnreg.h

129

#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)

sys/dev/pci/if_iwnreg.h

130

#define IWN5000_SCHED_CHAINEXT_EN (IWN_SCHED_BASE + 0x244)

sys/dev/pci/if_iwnreg.h

131

#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)