sys/dev/pci/drm/i915/gt/intel_ggtt.c

240

if (!IS_GEN9_LP(i915) && GRAPHICS_VER(i915) < 11)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

95

freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000;

sys/dev/pci/drm/i915/gt/intel_gtt.c

453

else if (IS_GEN9_LP(i915))

sys/dev/pci/drm/i915/gt/intel_gtt.c

688

else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))

sys/dev/pci/drm/i915/gt/intel_mocs.c

499

} else if (IS_GEN9_LP(i915)) {

sys/dev/pci/drm/i915/gt/intel_rc6.c

503

if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) {

sys/dev/pci/drm/i915/gt/intel_rc6.c

810

if (IS_GEN9_LP(i915)) {

sys/dev/pci/drm/i915/gt/intel_rps.c

1113

if (IS_GEN9_LP(i915))

sys/dev/pci/drm/i915/gt/intel_rps.c

1145

if (IS_GEN9_LP(i915)) {

sys/dev/pci/drm/i915/gt/intel_rps.c

2289

if (IS_GEN9_LP(i915))

sys/dev/pci/drm/i915/gt/intel_sseu.c

388

intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3,

sys/dev/pci/drm/i915/gt/intel_sseu.c

389

IS_GEN9_LP(i915) ? 3 : 4, 8);

sys/dev/pci/drm/i915/gt/intel_sseu.c

458

!IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;

sys/dev/pci/drm/i915/gt/intel_sseu.c

460

IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1;

sys/dev/pci/drm/i915/gt/intel_sseu.c

463

if (IS_GEN9_LP(i915)) {

sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c

148

if (IS_GEN9_LP(gt->i915)) {

sys/dev/pci/drm/i915/gt/intel_wopcm.c

96

if (IS_GEN9_LP(i915))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2486

if (IS_GEN9_LP(i915))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

542

if (IS_GEN9_LP(i915))

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

38

if (IS_GEN9_LP(uncore->i915))

sys/dev/pci/drm/i915/i915_drv.h

632

#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915))