sys/arch/arm/cortex/ampintc.c

71

#define ICD_ISRn(i) (0x080 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm/cortex/ampintc.c

72

#define ICD_ISERn(i) (0x100 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm/cortex/ampintc.c

73

#define ICD_ICERn(i) (0x180 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm/cortex/ampintc.c

74

#define ICD_ISPRn(i) (0x200 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm/cortex/ampintc.c

75

#define ICD_ICPRn(i) (0x280 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm/cortex/ampintc.c

76

#define ICD_ABRn(i) (0x300 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/agintc.c

82

#define GICD_IGROUPR(i) (0x0080 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/agintc.c

83

#define GICD_ISENABLER(i) (0x0100 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/agintc.c

84

#define GICD_ICENABLER(i) (0x0180 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/agintc.c

85

#define GICD_ISPENDR(i) (0x0200 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/agintc.c

86

#define GICD_ICPENDR(i) (0x0280 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/agintc.c

87

#define GICD_ISACTIVER(i) (0x0300 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/agintc.c

88

#define GICD_ICACTIVER(i) (0x0380 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/agintc.c

94

#define GICD_IGRPMODR(i) (0x0d00 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/ampintc.c

73

#define ICD_ISRn(i) (0x080 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/ampintc.c

74

#define ICD_ISERn(i) (0x100 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/ampintc.c

75

#define ICD_ICERn(i) (0x180 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/ampintc.c

76

#define ICD_ISPRn(i) (0x200 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/ampintc.c

77

#define ICD_ICPRn(i) (0x280 + (IRQ_TO_REG32(i) * 4))

sys/arch/arm64/dev/ampintc.c

78

#define ICD_ABRn(i) (0x300 + (IRQ_TO_REG32(i) * 4))