sys/dev/pci/drm/i915/display/hsw_ips.c

286

crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;

sys/dev/pci/drm/i915/display/hsw_ips.c

356

if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)

sys/dev/pci/drm/i915/display/hsw_ips.c

51

intel_de_write(display, IPS_CTL, val);

sys/dev/pci/drm/i915/display/hsw_ips.c

59

if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))

sys/dev/pci/drm/i915/display/hsw_ips.c

81

if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))

sys/dev/pci/drm/i915/display/hsw_ips.c

85

intel_de_write(display, IPS_CTL, 0);

sys/dev/pci/drm/i915/display/hsw_ips.c

86

intel_de_posting_read(display, IPS_CTL);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

438

MMIO_D(IPS_CTL);