sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1356

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1389

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1210

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1243

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1932

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1944

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

888

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

892

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

926

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

935

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/radeon/evergreen.c

4476

WREG32(INT_MASK + crtc_offsets[i], 0);

sys/dev/pci/drm/radeon/evergreen.c

4576

rdev, INT_MASK + crtc_offsets[i],

sys/dev/pci/drm/radeon/si.c

5945

WREG32(INT_MASK + crtc_offsets[i], 0);

sys/dev/pci/drm/radeon/si.c

6099

rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK,