sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2109

u8 lane = INTEL_CX0_LANE0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2144

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2148

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2149

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2155

intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2444

cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2450

INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2454

INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2462

INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2466

INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2475

INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2479

INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2487

INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2491

INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2641

cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2650

intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2658

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2662

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2670

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2674

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2683

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2687

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2694

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2698

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2900

u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2979

u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3028

INTEL_CX0_LANE0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3268

u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3350

u8 lane = dig_port->lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

35

#define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

492

u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

76

? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;