sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2138

intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2152

intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2722

intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2829

intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2844

intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2901

u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2904

u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2939

intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3044

intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3081

intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3086

intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3302

intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3315

intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3316

intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3325

intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3326

intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

57

if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) ||

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

69

return INTEL_CX0_BOTH_LANES;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

76

? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

93

for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)