AQ_READ_REG
ver = AQ_READ_REG(sc, AQ_FW_VERSION_REG);
v = AQ_READ_REG(sc, FW_MPI_DAISY_CHAIN_STATUS_REG);
boot_exit_code = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG);
rbl_status = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG) & 0xffff;
v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG);
flb_status = AQ_READ_REG(sc,
if (AQ_READ_REG(sc, AQ_FW_VERSION_REG) != 0)
v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG);
sc->sc_fw_version = AQ_READ_REG(sc, AQ_FW_VERSION_REG);
uint32_t hwrev = AQ_READ_REG(sc, AQ_HW_REVISION_REG);
if (AQ_READ_REG(sc, FW1X_MPI_INIT2_REG) == 0) {
sc->sc_mbox_addr = AQ_READ_REG(sc, FW_MPI_MBOX_ADDR_REG);
tid0 = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG);
*data = AQ_READ_REG(sc, reg);
tid1 = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG);
v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG);
v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG);
v = AQ_READ_REG(sc, AQ2_MCP_HOST_REQ_INT_REG);
v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG);
v = AQ_READ_REG(sc, AQ2_MCP_HOST_REQ_INT_REG);
v = AQ_READ_REG(sc, AQ_HW_REVISION_REG);
(AQ_READ_REG(sc, AQ_INTR_CTRL_REG) & AQ_INTR_CTRL_RESET_IRQ) == 0,
efuse_shadow_addr = AQ_READ_REG(sc, FW2X_MPI_EFUSEADDR_REG);
efuse_shadow_addr = AQ_READ_REG(sc, FW1X_MPI_EFUSEADDR_REG);
WAIT_FOR(AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG) == 1, 1, 10000, &error);
v = AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG);
WAIT_FOR(AQ_READ_REG(sc, AQ_FW_MBOX_ADDR_REG) != addr,
WAIT_FOR((AQ_READ_REG(sc, AQ_FW_MBOX_CMD_REG) &
*p++ = AQ_READ_REG(sc, AQ_FW_MBOX_VAL_REG);
WAIT_FOR((AQ_READ_REG(sc, AQ2_MIF_HOST_FINISHED_STATUS_READ_REG) &
v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG);
v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG);
v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG);
v = AQ_READ_REG(sc, AQ_PCI_REG_CONTROL_6_REG);
fpgaver = AQ_READ_REG(sc, AQ2_HW_FPGA_VERSION_REG);
WAIT_FOR((AQ_READ_REG(sc, RPF_RSS_KEY_ADDR_REG) &
WAIT_FOR((AQ_READ_REG(sc, RPF_RSS_REDIR_ADDR_REG) &
tx->tx_prod = AQ_READ_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(tx->tx_q));
rx->rx_cons = AQ_READ_REG(sc, RX_DMA_DESC_HEAD_PTR_REG(rx->rx_q)) &
end = AQ_READ_REG(sc, RX_DMA_DESC_HEAD_PTR_REG(rx->rx_q)) &
end = AQ_READ_REG(sc, TX_DMA_DESC_HEAD_PTR_REG(tx->tx_q)) &
status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
cache = AQ_READ_REG(sc, RX_DMA_DESC_CACHE_INIT_REG);
WAIT_FOR(AQ_READ_REG(sc, AQ2_ART_SEM_REG) == 1, 10, 1000, &error);
(AQ_READ_REG(sc, AQ_SMB_BUS_REG) & AQ_SMB_BUS_XFER_COMPLETE) != 0,
if ((AQ_READ_REG(sc, AQ_SMB_BUS_REG) & AQ_SMB_BUS_RX_ACK) != ack)
WAIT_FOR((AQ_READ_REG(sc, AQ_SMB_BUS_REG) & AQ_SMB_BUS_BUSY) == 0,
if ((AQ_READ_REG(sc, AQ_SMB_BUS_REG) & AQ_SMB_BUS_REPEAT_DETECT) == 0) {
sff->sff_data[i] = AQ_READ_REG(sc, AQ_SMB_RX_DATA_REG);
sff->sff_data[i] = AQ_READ_REG(sc, AQ_SMB_RX_DATA_REG);
_v = AQ_READ_REG((sc), (reg)); \
((uint64_t)AQ_READ_REG(sc, reg) | \
(((uint64_t)AQ_READ_REG(sc, (reg) + 4)) << 32))