IDEDMA_TBL
IDEDMA_TBL(chan), val);
sl->regs[chan].dma_iohs[IDEDMA_TBL(0)], 0, val);
&ps->regs[channel].dma_iohs[IDEDMA_TBL(0)]) != 0) {
ps->regs[channel].dma_iohs[IDEDMA_TBL(0)], 0,
(chan << 8) + SVWSATA_DMA + IDEDMA_TBL(0), val);