Symbol: I915_NUM_ENGINES
sys/dev/pci/drm/i915/gem/i915_gem_context.c
1126
const unsigned int max = I915_NUM_ENGINES;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1706
static const i915_reg_t _reg[I915_NUM_ENGINES] = {
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
478
BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
968
GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
198
} nodes[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gt/intel_gt.c
516
struct i915_request *requests[I915_NUM_ENGINES] = {};
sys/dev/pci/drm/i915/gt/intel_gt.h
187
(id__) < I915_NUM_ENGINES; \
sys/dev/pci/drm/i915/gt/intel_gt_types.h
205
struct intel_engine_cs *engine[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gt/intel_reset.c
1646
BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
sys/dev/pci/drm/i915/gt/mock_engine.c
347
GEM_BUG_ON(id >= I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3557
struct kthread_worker *worker[I915_NUM_ENGINES] = {};
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3564
arg = kmalloc_array(I915_NUM_ENGINES, sizeof(*arg), GFP_KERNEL);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3568
memset(arg, 0, I915_NUM_ENGINES * sizeof(*arg));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1012
memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
989
threads = kmalloc_array(I915_NUM_ENGINES, sizeof(*threads), GFP_KERNEL);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
284
return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
539
timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
sys/dev/pci/drm/i915/gt/selftest_timeline.c
614
timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
34
} engine[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
202
u32 ads_regset_count[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5939
BUILD_BUG_ON(ilog2(VIRTUAL_ENGINES) < I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
599
static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
sys/dev/pci/drm/i915/gvt/gvt.h
151
struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/gvt.h
152
struct list_head workload_q_head[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/gvt.h
153
struct intel_context *shadow[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/gvt.h
160
DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gvt/gvt.h
161
DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gvt/gvt.h
162
void *ring_scan_buffer[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/gvt.h
163
int ring_scan_buffer_size[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/gvt.h
171
} last_ctx[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/gvt.h
209
u32 hws_pga[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/gvt.h
340
struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/gvt.h
358
int ctx_mmio_count[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/mmio_context.c
164
u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
sys/dev/pci/drm/i915/gvt/scheduler.c
1421
bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gvt/scheduler.c
1436
bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gvt/scheduler.h
47
struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/scheduler.h
52
struct intel_vgpu *engine_owner[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/scheduler.h
55
struct task_struct *thread[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/scheduler.h
56
wait_queue_head_t waitq[I915_NUM_ENGINES];
sys/dev/pci/drm/i915/gvt/vgpu.c
281
for (i = 0; i < I915_NUM_ENGINES; i++)
sys/dev/pci/drm/i915/intel_device_info.c
400
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
sys/dev/pci/drm/i915/selftests/igt_live_test.h
21
unsigned int reset_engine[I915_MAX_GT][I915_NUM_ENGINES];