Symbol: APMU_EMAC0_CLK_RST_CTRL
sys/arch/riscv64/dev/smtclock.c
349
{ K1_CLK_EMAC0_BUS, APMU_EMAC0_CLK_RST_CTRL, 0 },
sys/arch/riscv64/dev/smtclock.c
370
{ K1_RESET_EMAC0, APMU_EMAC0_CLK_RST_CTRL, -1, 1 },
sys/arch/riscv64/dev/smtclock.c
442
{ K3_CLK_EMAC0_BUS, APMU_EMAC0_CLK_RST_CTRL, 0 },
sys/arch/riscv64/dev/smtclock.c
443
{ K3_CLK_EMAC0_RGMII_TX, APMU_EMAC0_CLK_RST_CTRL, 8 },
sys/arch/riscv64/dev/smtclock.c
470
{ K3_RESET_EMAC0, APMU_EMAC0_CLK_RST_CTRL, -1, 1 },