sys/arch/riscv64/dev/smtclock.c

208

{ K1_CLK_PCIE0_MASTER, APMU_PCIE_CLK_RES_CTRL_PORTA, 2 },

sys/arch/riscv64/dev/smtclock.c

209

{ K1_CLK_PCIE0_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTA, 1 },

sys/arch/riscv64/dev/smtclock.c

210

{ K1_CLK_PCIE0_DBI, APMU_PCIE_CLK_RES_CTRL_PORTA, 0 },

sys/arch/riscv64/dev/smtclock.c

224

{ K1_RESET_PCIE0_MASTER, APMU_PCIE_CLK_RES_CTRL_PORTA, -1, 5 },

sys/arch/riscv64/dev/smtclock.c

225

{ K1_RESET_PCIE0_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTA, -1, 4 },

sys/arch/riscv64/dev/smtclock.c

226

{ K1_RESET_PCIE0_DBI, APMU_PCIE_CLK_RES_CTRL_PORTA, -1, 3 },

sys/arch/riscv64/dev/smtclock.c

227

{ K1_RESET_PCIE0_GLOBAL, APMU_PCIE_CLK_RES_CTRL_PORTA, 8, -1 },

sys/arch/riscv64/dev/smtcomphy.c

177

val = regmap_read_4(sc->sc_apmu, APMU_PCIE_CLK_RES_CTRL_PORTA);

sys/arch/riscv64/dev/smtcomphy.c

179

regmap_write_4(sc->sc_apmu, APMU_PCIE_CLK_RES_CTRL_PORTA, val);