sys/arch/armv7/exynos/exiic.c

230

HWRITE4(sc, I2C_STAT, 0);

sys/arch/armv7/exynos/exiic.c

232

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_TX

sys/arch/armv7/exynos/exiic.c

261

if (exiic_wait_state(sc, I2C_STAT, I2C_STAT_BUSY_SIGNAL, 0)) {

sys/arch/armv7/exynos/exiic.c

272

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_TX

sys/arch/armv7/exynos/exiic.c

276

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX

sys/arch/armv7/exynos/exiic.c

301

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX

sys/arch/armv7/exynos/exiic.c

331

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX

sys/arch/armv7/exynos/exiic.c

350

return (HREAD4(sc, I2C_STAT) & I2C_STAT_LAST_RVCD_BIT) ?