sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
262
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
263
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
264
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
265
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
266
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
267
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
268
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
269
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
270
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
271
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
272
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
273
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
274
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
275
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
276
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
277
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
278
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
279
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
280
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
281
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
282
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
283
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
284
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
285
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
286
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
287
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
288
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
289
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
290
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
291
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
292
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
293
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
294
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
295
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
296
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
297
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
298
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
299
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
300
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
301
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
302
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
303
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
304
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
305
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
306
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
307
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
308
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
309
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
310
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
311
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
312
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
313
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
314
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
315
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
316
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
317
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
318
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
319
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
320
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
321
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
322
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
323
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
324
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
325
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
326
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
327
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
328
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
329
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
330
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
331
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
332
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
333
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
334
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
335
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
336
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
337
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
338
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
339
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
340
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
341
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
342
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
343
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
344
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
345
HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_STATUS, PIPE_READ_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
346
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
347
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
348
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
349
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
350
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
351
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
352
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
353
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
354
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
355
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
356
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
357
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
358
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
359
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
360
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
361
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
362
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
363
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
364
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
365
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
366
HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
367
HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
368
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
369
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
370
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
371
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
372
HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
373
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
374
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
375
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
376
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
377
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
378
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
379
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
380
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
381
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
382
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
383
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
384
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
385
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
386
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
387
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
388
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
389
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
390
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
391
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
392
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
393
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
397
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
398
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
399
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
407
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
408
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
409
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
410
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
411
HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
412
HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
413
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
414
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
415
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
416
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
421
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
422
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
423
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
424
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
425
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
426
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
427
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
428
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
429
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
430
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
431
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
432
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
433
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
434
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
435
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
436
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
437
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
438
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
439
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
440
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
441
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
442
HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
443
HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
444
HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
445
HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
446
HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
447
HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
448
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
449
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
450
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
451
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
452
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
453
HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
454
HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
455
HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
456
HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
457
HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
100
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
101
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
102
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
103
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
104
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
105
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
106
HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
107
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
108
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
109
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
110
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
111
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
112
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
113
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
114
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
115
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
116
HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
121
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
122
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
123
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
128
HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
129
HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
130
HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
72
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
73
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
74
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
75
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
76
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
77
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
78
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
79
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
80
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
81
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
82
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
83
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
84
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
85
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
86
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
87
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
88
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
89
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
90
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
91
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
92
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
93
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
94
HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
95
HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
96
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
97
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
98
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
99
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
60
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
61
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
62
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
63
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
64
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
65
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
66
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
67
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
68
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
69
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
70
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
71
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
72
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
73
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
74
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
75
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
76
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
77
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
78
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
79
HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
80
HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
81
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
82
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
83
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
84
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
85
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
86
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
87
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
88
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
89
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
90
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
91
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
92
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
93
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
94
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
95
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
96
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
102
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
47
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
48
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
49
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
50
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
51
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
52
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
53
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
54
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
55
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
56
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
57
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
58
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
59
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
60
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
61
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
62
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
63
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
64
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
65
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
66
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
67
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
68
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
69
HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
70
HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
71
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
72
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
73
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
74
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
75
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
76
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
77
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
78
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
79
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
80
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
81
HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
82
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
83
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
84
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
85
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
86
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
87
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
88
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
89
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
90
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
91
HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
92
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
93
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
94
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
95
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
96
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
97
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
98
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
100
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
101
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
102
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
103
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
104
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
105
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
106
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
107
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
108
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
109
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
110
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
111
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
112
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
113
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
114
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
115
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
116
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
117
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
118
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
119
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
120
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
121
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
122
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
123
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
124
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
125
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
126
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
127
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
128
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
129
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
130
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
131
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
132
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
133
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
134
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
135
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
136
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
137
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
138
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
139
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
140
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
141
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_Y_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
142
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_ALPHA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
143
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, PACK_3TO2_ELEMENT_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
144
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
145
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
146
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
147
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
148
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
149
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
150
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
151
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
152
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
153
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
154
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
155
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
156
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
157
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
158
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
159
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
160
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
161
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
162
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
163
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
164
HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
165
HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
166
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
167
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
168
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
169
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
170
HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
171
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
172
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
173
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
174
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
175
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
176
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
177
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
178
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
179
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
180
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
181
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
182
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
183
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
184
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
185
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
186
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
187
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, ROW_TTU_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
188
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
189
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
190
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
191
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
192
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
194
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
195
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
196
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
197
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
198
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
199
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
200
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
201
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
202
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
203
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
204
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
205
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
206
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
207
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
208
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
209
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
210
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
211
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
212
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
213
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
214
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
215
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
216
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
217
HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
218
HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
219
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
220
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
221
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
222
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
223
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
224
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
225
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
226
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
227
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
228
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
229
HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
230
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
231
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
232
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
233
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
234
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
235
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
236
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
237
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
238
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
239
HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
240
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
241
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
242
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
243
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
244
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
245
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
246
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
247
HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
39
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
40
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
41
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
42
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
43
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
44
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
45
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
46
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
47
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
51
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
52
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
53
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
54
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
55
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
56
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
57
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
58
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
59
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
60
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
61
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
62
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
63
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
64
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
65
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
66
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
67
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
68
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
69
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
70
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
71
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
72
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
73
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
74
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
75
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
76
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
77
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
78
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
79
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
80
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
81
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
82
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
83
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
84
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
85
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
86
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
87
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
88
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
89
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
90
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
91
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
92
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
93
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
94
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
95
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
96
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
97
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
98
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
99
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
100
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
101
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
102
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
103
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
104
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
105
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
106
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
107
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
108
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
109
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
110
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
111
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
112
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
113
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
114
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
115
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
116
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
117
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
118
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
119
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
120
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
121
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
122
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
123
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
124
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
125
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_Y_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
126
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_ALPHA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
127
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, PACK_3TO2_ELEMENT_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
128
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
129
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
130
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
131
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
132
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
133
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
134
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
135
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
136
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
137
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
138
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
139
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
140
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
141
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
142
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
143
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
144
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
145
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
146
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
147
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
148
HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
149
HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
150
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
151
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
152
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
153
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
154
HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
155
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
156
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
157
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
158
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
159
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
160
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
161
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
162
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
163
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
164
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
165
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
166
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
167
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
168
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
169
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
170
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
171
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, ROW_TTU_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
172
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
173
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
174
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
175
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
176
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
178
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
179
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
180
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
181
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
182
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
183
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
184
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
185
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
186
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
187
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
188
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
189
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
190
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
191
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
192
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
193
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_REQ_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
194
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
195
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
196
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
197
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
198
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
199
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
200
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
201
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
202
HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
203
HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
204
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
205
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
206
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
207
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
208
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
209
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
210
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
211
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
212
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
213
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
214
HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
215
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
216
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
217
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
218
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
219
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
220
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
221
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
222
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
223
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
224
HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
225
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
226
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
227
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
228
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
229
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
230
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
231
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
232
HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
233
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
34
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
35
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
36
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
37
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
38
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
39
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
40
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
41
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
42
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
43
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
44
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
45
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
46
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
47
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
48
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
49
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
50
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
51
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
52
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
53
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
54
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
55
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
56
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
57
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
58
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
59
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
60
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
61
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
62
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
63
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
64
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
65
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
66
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
67
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
68
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
69
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
70
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
71
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
72
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
73
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
74
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
75
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
76
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
77
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
78
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
79
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
80
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
81
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
82
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
83
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
84
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
85
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
86
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
87
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
88
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
89
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
90
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
91
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
92
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
93
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
94
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
95
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
96
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
97
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
98
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
99
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
36
HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
37
HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
38
HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, VMPG_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
39
HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, PTE_BUFFER_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
40
HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, BIGK_FRAGMENT_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
41
HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
42
HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
43
HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_VALUE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
44
HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
45
HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_VALUE, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h
34
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
100
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
101
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
102
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
103
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
104
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
105
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
106
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
107
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
108
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
109
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
110
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
111
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
112
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
113
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
114
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
115
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
116
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_Y_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
117
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_ALPHA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
118
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, PACK_3TO2_ELEMENT_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
119
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
120
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
121
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
122
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
123
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
124
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
125
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
126
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
127
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
128
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
129
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
130
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
131
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
132
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
133
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
134
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
135
HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
136
HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
137
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
138
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
139
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
140
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
141
HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
142
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
143
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
144
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
145
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
146
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
147
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
148
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
149
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
150
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
151
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
152
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
153
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
154
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
155
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
156
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
157
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
158
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, ROW_TTU_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
159
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
160
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
161
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
162
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
163
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
165
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
166
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
167
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
168
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
169
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
170
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
171
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
172
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
173
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
174
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
175
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
176
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
177
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
178
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
179
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
180
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_REQ_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
181
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
182
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
183
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
184
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
185
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
186
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
187
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
188
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
189
HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
190
HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
191
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
192
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
193
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
194
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
195
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
196
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
197
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
198
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
199
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
200
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
201
HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
202
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
203
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
204
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
205
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
206
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
207
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
208
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
209
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
210
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
211
HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
212
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
213
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
214
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
215
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
216
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
217
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
218
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
219
HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
220
HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
221
HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, VMPG_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
222
HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, PTE_BUFFER_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
223
HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, BIGK_FRAGMENT_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
224
HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
225
HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
226
HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_VALUE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
227
HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
228
HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_VALUE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
229
HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, MALL_PREF_CMD_TYPE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
230
HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, MALL_PREF_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
231
HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
232
HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
233
HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
234
HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_SCALE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
235
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
236
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
237
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
238
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
239
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
240
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_Y_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
241
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_CB_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
242
HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_CR_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
243
HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
244
HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW, HUBP_3DLUT_ADDRESS_LOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
245
HUBP_SF(CURSOR0_0_HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
246
HUBP_SF(HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, VIEWPORT_MCACHE_SPLIT_COORDINATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
247
HUBP_SF(HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, VIEWPORT_MCACHE_SPLIT_COORDINATE_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
248
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_REG_READ_1H_P0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
249
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_REG_READ_2H_P0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
250
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_REG_READ_1H_P1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
251
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_REG_READ_2H_P1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
252
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
253
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
254
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
255
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
256
HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
257
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh)
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
45
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
46
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
47
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
48
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
49
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
50
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
51
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
52
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
53
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
54
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
55
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
56
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
57
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
58
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
59
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
60
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
61
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
62
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
63
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
64
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
65
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
66
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
67
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
68
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
69
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
70
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
71
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
72
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
73
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
74
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
75
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
76
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
77
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
78
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
79
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
80
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
81
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
82
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
83
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
84
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
85
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
86
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
87
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
88
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
89
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
90
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
91
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
92
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
93
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
94
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
95
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
96
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
97
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
98
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
99
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
