sys/arch/armv7/omap/ommmc.c

489

sc->regs[i] = HREAD1(sc, i);

sys/dev/fdt/plgpio.c

130

reg = HREAD1(sc, GPIODATA(pin));

sys/dev/fdt/plgpio.c

39

HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits))

sys/dev/fdt/plgpio.c

41

HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits))

sys/dev/ic/imxiic.c

137

if (((state = HREAD1(sc, I2C_I2SR)) & mask) == value)

sys/dev/ic/imxiic.c

166

if (HREAD1(sc, I2C_I2SR) & I2C_I2SR_RXAK)

sys/dev/ic/imxiic.c

174

HREAD1(sc, I2C_I2DR);

sys/dev/ic/imxiic.c

188

((uint8_t*)data)[i] = HREAD1(sc, I2C_I2DR);

sys/dev/ic/imxiic.c

206

if (HREAD1(sc, I2C_I2SR) & I2C_I2SR_RXAK)

sys/dev/ic/imxiic.c

214

if (HREAD1(sc, I2C_I2SR) & I2C_I2SR_RXAK)

sys/dev/ic/imxiic.c

223

if (HREAD1(sc, I2C_I2SR) & I2C_I2SR_RXAK)

sys/dev/ic/imxiic.c

67

HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits))

sys/dev/ic/imxiic.c

69

HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits))

sys/dev/sdmmc/sdhc.c

1213

if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))

sys/dev/sdmmc/sdhc.c

1220

HREAD1(hp, SDHC_SOFTWARE_RESET)));

sys/dev/sdmmc/sdhc.c

1411

HREAD1(hp, SDHC_POWER_CTL));

sys/dev/sdmmc/sdhc.c

467

hp->regs[i] = HREAD1(hp, i);

sys/dev/sdmmc/sdhc.c

621

if (HREAD1(hp, SDHC_POWER_CTL) ==

sys/dev/sdmmc/sdhc.c

646

if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) {

sys/dev/sdmmc/sdhc.c

784

reg = HREAD1(hp, SDHC_HOST_CTL);

sys/dev/sdmmc/sdhc.c

86

HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))

sys/dev/sdmmc/sdhc.c

90

HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))

sys/dev/sdmmc/sdhc.c

912

*p++ = HREAD1(hp, SDHC_RESPONSE + i);