Symbol: HDMI_INFOFRAME_CONTROL1
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1647
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1725
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1553
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1666
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
641
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
755
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
146
SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
154
SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
674
uint32_t HDMI_INFOFRAME_CONTROL1;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
73
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
593
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
157
uint32_t HDMI_INFOFRAME_CONTROL1;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
64
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
703
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
66
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
268
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
67
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
226
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
214
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
65
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
225
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
280
SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
98
SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
192
SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/pci/drm/radeon/evergreen_hdmi.c
224
WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,