sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1635

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1637

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1719

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1721

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1659

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1660

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1661

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1662

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1674

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1675

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1676

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1677

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

637

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

751

REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

759

REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

144

SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

152

SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

153

SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

673

uint32_t HDMI_INFOFRAME_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

72

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

589

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

156

uint32_t HDMI_INFOFRAME_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

63

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

696

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

65

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

261

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

66

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

219

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

207

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

64

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

218

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

279

SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

97

SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

191

SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/radeon/evergreen_hdmi.c

416

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,

sys/dev/pci/drm/radeon/evergreen_hdmi.c

424

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,

sys/dev/pci/drm/radeon/evergreen_hdmi.c

433

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);