sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1630

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1473

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

630

HDMI_GC_CONT, 1,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

140

SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

225

SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

409

uint8_t HDMI_GC_CONT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

541

uint32_t HDMI_GC_CONT;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

582

HDMI_GC_CONT, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

213

SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

420

type HDMI_GC_CONT;\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

687

HDMI_GC_CONT, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

124

SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

252

HDMI_GC_CONT, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

123

SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

210

HDMI_GC_CONT, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h

44

SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

198

HDMI_GC_CONT, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

124

SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

210

HDMI_GC_CONT, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

45

SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

sys/dev/pci/drm/radeon/evergreen_hdmi.c

316

HDMI_GC_CONT); /* send general control packets every frame */