sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1645

tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1019

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

644

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

147

SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

668

uint32_t HDMI_GC;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

69

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1038

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

596

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

149

uint32_t HDMI_GC;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

58

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

707

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

53

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

272

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

54

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

230

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

218

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

52

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

229

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

267

SRI_ARR(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

85

SRI_ARR(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

179

SRI_ARR(HDMI_GC, DIG, id), \

sys/dev/pci/drm/radeon/evergreen_hdmi.c

397

WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);

sys/dev/pci/drm/radeon/evergreen_hdmi.c

399

WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);