Symbol: HDMI_CONTROL
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1607
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1608
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1613
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1614
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1619
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1620
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1029
REG_UPDATE_5(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1036
REG_UPDATE_3(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
557
REG_UPDATE_3(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
562
REG_UPDATE_5(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
572
REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
576
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
580
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
587
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
591
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
597
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
611
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
623
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
136
SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
137
SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
138
SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
139
SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
298
SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
299
SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
308
SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
309
SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
667
uint32_t HDMI_CONTROL;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
68
SRI(HDMI_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1046
REG_UPDATE_5(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
503
REG_UPDATE_6(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
514
REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
519
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
525
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
534
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
540
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
548
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
563
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
575
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
148
uint32_t HDMI_CONTROL;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
56
SRI(HDMI_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
618
REG_UPDATE_6(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
629
REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
633
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
637
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
644
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
648
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
654
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
667
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
679
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
51
SRI(HDMI_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
183
REG_UPDATE_6(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
194
REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
198
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
202
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
209
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
213
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
219
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
232
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
244
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
52
SRI(HDMI_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
141
REG_UPDATE_6(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
152
REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
156
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
160
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
167
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
171
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
177
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
190
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
202
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
129
REG_UPDATE_6(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
140
REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
144
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
148
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
155
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
159
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
165
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
178
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
190
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
221
REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
224
REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
227
REG_UPDATE(HDMI_CONTROL, TMDS_COLOR_FORMAT, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
50
SRI(HDMI_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
141
REG_UPDATE_6(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
152
REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
156
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
160
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
167
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
171
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
177
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
190
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
202
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
822
REG_UPDATE(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
838
REG_UPDATE(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
849
REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
852
REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
855
REG_UPDATE(HDMI_CONTROL, TMDS_COLOR_FORMAT, 0);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
266
SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
83
SRI_ARR(HDMI_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
178
SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \
sys/dev/pci/drm/radeon/evergreen_hdmi.c
326
val = RREG32(HDMI_CONTROL + offset);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
353
WREG32(HDMI_CONTROL + offset, val);