Symbol: HDMI_AUDIO_PACKET_CONTROL
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1654
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1656
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1626
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1627
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1269
REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
174
SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
175
SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
676
uint32_t HDMI_AUDIO_PACKET_CONTROL;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
75
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1256
REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
159
uint32_t HDMI_AUDIO_PACKET_CONTROL;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
66
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
770
REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
68
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
69
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
67
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
282
SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
100
SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
194
SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \
sys/dev/pci/drm/radeon/evergreen_hdmi.c
381
WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,