Symbol: HDMI_ACR_SOURCE
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1667
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1670
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1489
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1284
HDMI_ACR_SOURCE, 0,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
180
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
258
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
452
uint8_t HDMI_ACR_SOURCE;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
584
uint32_t HDMI_ACR_SOURCE;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1270
HDMI_ACR_SOURCE, 0,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
250
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
466
type HDMI_ACR_SOURCE;\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
776
HDMI_ACR_SOURCE, 0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
154
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
154
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h
75
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
155
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
77
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/radeon/evergreen_hdmi.c
86
HDMI_ACR_SOURCE | /* select SW CTS value */