Symbol: HDMI_ACR_PACKET_CONTROL
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1667
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1670
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1672
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1488
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1489
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1282
REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
179
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
180
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
181
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
677
uint32_t HDMI_ACR_PACKET_CONTROL;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
76
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1268
REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
160
uint32_t HDMI_ACR_PACKET_CONTROL;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
67
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
774
REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
69
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
70
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
68
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
283
SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
101
SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
195
SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \
sys/dev/pci/drm/radeon/evergreen_hdmi.c
82
WREG32(HDMI_ACR_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
85
WREG32(HDMI_ACR_PACKET_CONTROL + offset,