Symbol: HDMI_ACR_N_44
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1496
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1504
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1308
REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
185
SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
263
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
457
uint8_t HDMI_ACR_N_44;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
589
uint32_t HDMI_ACR_N_44;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1294
REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
255
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
471
type HDMI_ACR_N_44;\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
800
REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
159
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
159
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h
80
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
160
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
82
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\