Symbol: HDMI_ACR_N_32
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1489
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1497
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1302
REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
183
SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
261
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
455
uint8_t HDMI_ACR_N_32;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
587
uint32_t HDMI_ACR_N_32;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1288
REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
253
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
469
type HDMI_ACR_N_32;\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
794
REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
157
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
157
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h
78
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
158
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
80
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\