Symbol: HDMI_ACR_CTS_32
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1486
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1494
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1299
REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
182
SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
260
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
454
uint8_t HDMI_ACR_CTS_32;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
586
uint32_t HDMI_ACR_CTS_32;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1285
REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
252
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
468
type HDMI_ACR_CTS_32;\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
791
REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
156
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
156
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h
77
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
157
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
79
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/radeon/evergreen_hdmi.c
89
WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));