Symbol: HDMI_ACR_48_0
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1500
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1508
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1311
REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
186
SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
682
uint32_t HDMI_ACR_48_0;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
81
SRI(HDMI_ACR_48_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1297
REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
165
uint32_t HDMI_ACR_48_0;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
72
SRI(HDMI_ACR_48_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
803
REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
74
SRI(HDMI_ACR_48_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
75
SRI(HDMI_ACR_48_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
73
SRI(HDMI_ACR_48_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
286
SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
106
SRI_ARR(HDMI_ACR_48_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
198
SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \
sys/dev/pci/drm/radeon/evergreen_hdmi.c
95
WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));