Symbol: HDMI_ACR_44_1
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1496
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1504
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1308
REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
185
SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
681
uint32_t HDMI_ACR_44_1;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
80
SRI(HDMI_ACR_44_1, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1294
REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
164
uint32_t HDMI_ACR_44_1;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
71
SRI(HDMI_ACR_44_1, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
800
REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
73
SRI(HDMI_ACR_44_1, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
74
SRI(HDMI_ACR_44_1, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
72
SRI(HDMI_ACR_44_1, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
285
SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
105
SRI_ARR(HDMI_ACR_44_1, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
197
SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
sys/dev/pci/drm/radeon/evergreen_hdmi.c
93
WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);