Symbol: HDMI_ACR_32_0
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1486
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1494
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1299
REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
182
SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
678
uint32_t HDMI_ACR_32_0;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
77
SRI(HDMI_ACR_32_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1285
REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
161
uint32_t HDMI_ACR_32_0;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
68
SRI(HDMI_ACR_32_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
791
REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
70
SRI(HDMI_ACR_32_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
71
SRI(HDMI_ACR_32_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
69
SRI(HDMI_ACR_32_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
284
SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
102
SRI_ARR(HDMI_ACR_32_0, DIG, id),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
196
SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
sys/dev/pci/drm/radeon/evergreen_hdmi.c
89
WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));