sys/dev/ic/qwx.c

10449

ctrl_reg_val = sc->ops.read32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG +

sys/dev/ic/qwx.c

10454

sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG +

sys/dev/ic/qwx.c

10457

addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP +

sys/dev/ic/qwx.c

10490

ctrl_reg_val = sc->ops.read32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG +

sys/dev/ic/qwx.c

10493

sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG +

sys/dev/ic/qwx.c

21296

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(sc);

sys/dev/ic/qwx.c

21297

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP;

sys/dev/ic/qwx.c

21302

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(sc);

sys/dev/ic/qwx.c

21303

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP;

sys/dev/ic/qwx.c

21306

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(sc);

sys/dev/ic/qwx.c

21307

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP;

sys/dev/ic/qwz.c

19170

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB;

sys/dev/ic/qwz.c

19171

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP;

sys/dev/ic/qwz.c

19176

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(sc);

sys/dev/ic/qwz.c

19177

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP;

sys/dev/ic/qwz.c

19180

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(sc);

sys/dev/ic/qwz.c

19181

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP;

sys/dev/ic/qwz.c

7794

ctrl_reg_val = sc->ops.read32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG +

sys/dev/ic/qwz.c

7799

sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG +

sys/dev/ic/qwz.c

7802

addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP +

sys/dev/ic/qwz.c

7835

ctrl_reg_val = sc->ops.read32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG +

sys/dev/ic/qwz.c

7838

sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG +