sys/dev/ic/qwx.c

10003

HAL_SEQ_WCSS_UMAC_WBM_REG +

sys/dev/ic/qwx.c

10008

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0,

sys/dev/ic/qwx.c

10011

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1,

sys/dev/ic/qwx.c

10016

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR,

sys/dev/ic/qwx.c

10021

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_MISC_ADDR(sc),

sys/dev/ic/qwx.c

21340

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(sc);

sys/dev/ic/qwx.c

21341

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;

sys/dev/ic/qwx.c

21344

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_BASE_LSB(sc);

sys/dev/ic/qwx.c

21345

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP;

sys/dev/ic/qwx.c

21348

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(sc);

sys/dev/ic/qwx.c

21349

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;

sys/dev/ic/qwx.c

9973

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR,

sys/dev/ic/qwx.c

9977

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_SIZE_ADDR,

sys/dev/ic/qwx.c

9981

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_RING_BASE_LSB,

sys/dev/ic/qwx.c

9984

sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_WBM_REG +

sys/dev/ic/qwx.c

9993

HAL_SEQ_WCSS_UMAC_WBM_REG +

sys/dev/ic/qwx.c

9997

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1,

sys/dev/ic/qwz.c

19212

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(sc);

sys/dev/ic/qwz.c

19213

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;

sys/dev/ic/qwz.c

19217

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +

sys/dev/ic/qwz.c

19219

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP;

sys/dev/ic/qwz.c

19222

s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(sc);

sys/dev/ic/qwz.c

19223

s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;

sys/dev/ic/qwz.c

7410

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(sc),

sys/dev/ic/qwz.c

7414

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(sc),

sys/dev/ic/qwz.c

7418

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_RING_BASE_LSB(sc),

sys/dev/ic/qwz.c

7421

sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_WBM_REG +

sys/dev/ic/qwz.c

7430

HAL_SEQ_WCSS_UMAC_WBM_REG +

sys/dev/ic/qwz.c

7434

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(sc),

sys/dev/ic/qwz.c

7440

HAL_SEQ_WCSS_UMAC_WBM_REG +

sys/dev/ic/qwz.c

7445

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(sc),

sys/dev/ic/qwz.c

7448

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(sc),

sys/dev/ic/qwz.c

7453

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(sc),

sys/dev/ic/qwz.c

7460

HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_MISC_ADDR(sc),

sys/dev/ic/qwz.c

8311

uint32_t wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;