HAL_SEQ_WCSS_UMAC_CE0_SRC_REG
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc) + HAL_CE_DST_RING_BASE_LSB +
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc) + HAL_CE_DST_RING_HP +
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc);
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc);
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP;
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG;
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG;
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc)) <
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG) <