sys/dev/ic/dwqe.c

206

mode = dwqe_read(sc, GMAC_CHAN_CONTROL(0));

sys/dev/ic/dwqe.c

209

dwqe_write(sc, GMAC_CHAN_CONTROL(0), mode);

sys/dev/ic/dwqereg.h

211

#define GMAC_CHAN_RX_WATCHDOG(x) (GMAC_CHAN_CONTROL(x) + 0x38)

sys/dev/ic/dwqereg.h

212

#define GMAC_CHAN_SLOT_CTRL_STATUS(x) (GMAC_CHAN_CONTROL(x) + 0x3c)

sys/dev/ic/dwqereg.h

213

#define GMAC_CHAN_CUR_TX_DESC(x) (GMAC_CHAN_CONTROL(x) + 0x44)

sys/dev/ic/dwqereg.h

214

#define GMAC_CHAN_CUR_RX_DESC(x) (GMAC_CHAN_CONTROL(x) + 0x4c)

sys/dev/ic/dwqereg.h

215

#define GMAC_CHAN_CUR_TX_BUF_ADDR(x) (GMAC_CHAN_CONTROL(x) + 0x54)

sys/dev/ic/dwqereg.h

216

#define GMAC_CHAN_CUR_RX_BUF_ADDR(x) (GMAC_CHAN_CONTROL(x) + 0x5c)

sys/dev/ic/dwqereg.h

217

#define GMAC_CHAN_STATUS(x) (GMAC_CHAN_CONTROL(x) + 0x60)