Symbol: GLIU_MSR_BASE
sys/dev/pci/glxreg.h
100
#define GLIU_IOD_BM9 (GLIU_MSR_BASE + 0xe9)
sys/dev/pci/glxreg.h
101
#define GLIU_IOD_SC0 (GLIU_MSR_BASE + 0xea)
sys/dev/pci/glxreg.h
102
#define GLIU_IOD_SC1 (GLIU_MSR_BASE + 0xeb)
sys/dev/pci/glxreg.h
103
#define GLIU_IOD_SC2 (GLIU_MSR_BASE + 0xec)
sys/dev/pci/glxreg.h
104
#define GLIU_IOD_SC3 (GLIU_MSR_BASE + 0xed)
sys/dev/pci/glxreg.h
105
#define GLIU_IOD_SC4 (GLIU_MSR_BASE + 0xee)
sys/dev/pci/glxreg.h
106
#define GLIU_IOD_SC5 (GLIU_MSR_BASE + 0xef)
sys/dev/pci/glxreg.h
107
#define GLIU_IOD_SC6 (GLIU_MSR_BASE + 0xf0)
sys/dev/pci/glxreg.h
108
#define GLIU_IOD_SC7 (GLIU_MSR_BASE + 0xf1)
sys/dev/pci/glxreg.h
49
#define GLIU_GLD_MSR_CAP (GLIU_MSR_BASE + 0x00)
sys/dev/pci/glxreg.h
50
#define GLIU_GLD_MSR_CONFIG (GLIU_MSR_BASE + 0x01)
sys/dev/pci/glxreg.h
51
#define GLIU_GLD_MSR_SMI (GLIU_MSR_BASE + 0x02)
sys/dev/pci/glxreg.h
52
#define GLIU_GLD_MSR_ERROR (GLIU_MSR_BASE + 0x03)
sys/dev/pci/glxreg.h
53
#define GLIU_GLD_MSR_PM (GLIU_MSR_BASE + 0x04)
sys/dev/pci/glxreg.h
54
#define GLIU_GLD_MSR_DIAG (GLIU_MSR_BASE + 0x05)
sys/dev/pci/glxreg.h
56
#define GLIU_P2D_BM0 (GLIU_MSR_BASE + 0x20)
sys/dev/pci/glxreg.h
57
#define GLIU_P2D_BM1 (GLIU_MSR_BASE + 0x21)
sys/dev/pci/glxreg.h
58
#define GLIU_P2D_BM2 (GLIU_MSR_BASE + 0x22)
sys/dev/pci/glxreg.h
59
#define GLIU_P2D_BMK0 (GLIU_MSR_BASE + 0x23)
sys/dev/pci/glxreg.h
60
#define GLIU_P2D_BMK1 (GLIU_MSR_BASE + 0x24)
sys/dev/pci/glxreg.h
61
#define GLIU_P2D_BM3 (GLIU_MSR_BASE + 0x25)
sys/dev/pci/glxreg.h
62
#define GLIU_P2D_BM4 (GLIU_MSR_BASE + 0x26)
sys/dev/pci/glxreg.h
64
#define GLIU_COH (GLIU_MSR_BASE + 0x80)
sys/dev/pci/glxreg.h
65
#define GLIU_PAE (GLIU_MSR_BASE + 0x81)
sys/dev/pci/glxreg.h
66
#define GLIU_ARB (GLIU_MSR_BASE + 0x82)
sys/dev/pci/glxreg.h
67
#define GLIU_ASMI (GLIU_MSR_BASE + 0x83)
sys/dev/pci/glxreg.h
68
#define GLIU_AERR (GLIU_MSR_BASE + 0x84)
sys/dev/pci/glxreg.h
69
#define GLIU_DEBUG (GLIU_MSR_BASE + 0x85)
sys/dev/pci/glxreg.h
70
#define GLIU_PHY_CAP (GLIU_MSR_BASE + 0x86)
sys/dev/pci/glxreg.h
71
#define GLIU_NOUT_RESP (GLIU_MSR_BASE + 0x87)
sys/dev/pci/glxreg.h
72
#define GLIU_NOUT_WDATA (GLIU_MSR_BASE + 0x88)
sys/dev/pci/glxreg.h
73
#define GLIU_WHOAMI (GLIU_MSR_BASE + 0x8b)
sys/dev/pci/glxreg.h
74
#define GLIU_SLV_DIS (GLIU_MSR_BASE + 0x8c)
sys/dev/pci/glxreg.h
75
#define GLIU_STATISTIC_CNT0 (GLIU_MSR_BASE + 0xa0)
sys/dev/pci/glxreg.h
76
#define GLIU_STATISTIC_MASK0 (GLIU_MSR_BASE + 0xa1)
sys/dev/pci/glxreg.h
77
#define GLIU_STATISTIC_ACTION0 (GLIU_MSR_BASE + 0xa2)
sys/dev/pci/glxreg.h
78
#define GLIU_STATISTIC_CNT1 (GLIU_MSR_BASE + 0xa4)
sys/dev/pci/glxreg.h
79
#define GLIU_STATISTIC_MASK1 (GLIU_MSR_BASE + 0xa5)
sys/dev/pci/glxreg.h
80
#define GLIU_STATISTIC_ACTION1 (GLIU_MSR_BASE + 0xa6)
sys/dev/pci/glxreg.h
81
#define GLIU_STATISTIC_CNT2 (GLIU_MSR_BASE + 0xa8)
sys/dev/pci/glxreg.h
82
#define GLIU_STATISTIC_MASK2 (GLIU_MSR_BASE + 0xa9)
sys/dev/pci/glxreg.h
83
#define GLIU_STATISTIC_ACTION2 (GLIU_MSR_BASE + 0xaa)
sys/dev/pci/glxreg.h
84
#define GLIU_RQ_COMP_VAL (GLIU_MSR_BASE + 0xc0)
sys/dev/pci/glxreg.h
85
#define GLIU_RQ_COMP_MASK (GLIU_MSR_BASE + 0xc1)
sys/dev/pci/glxreg.h
86
#define GLIU_DA_COMP_VAL_LO (GLIU_MSR_BASE + 0xd0)
sys/dev/pci/glxreg.h
87
#define GLIU_DA_COMP_VAL_HI (GLIU_MSR_BASE + 0xd1)
sys/dev/pci/glxreg.h
88
#define GLIU_DA_COMP_MASK_LO (GLIU_MSR_BASE + 0xd2)
sys/dev/pci/glxreg.h
89
#define GLIU_DA_COMP_MASK_HI (GLIU_MSR_BASE + 0xd3)
sys/dev/pci/glxreg.h
91
#define GLIU_IOD_BM0 (GLIU_MSR_BASE + 0xe0)
sys/dev/pci/glxreg.h
92
#define GLIU_IOD_BM1 (GLIU_MSR_BASE + 0xe1)
sys/dev/pci/glxreg.h
93
#define GLIU_IOD_BM2 (GLIU_MSR_BASE + 0xe2)
sys/dev/pci/glxreg.h
94
#define GLIU_IOD_BM3 (GLIU_MSR_BASE + 0xe3)
sys/dev/pci/glxreg.h
95
#define GLIU_IOD_BM4 (GLIU_MSR_BASE + 0xe4)
sys/dev/pci/glxreg.h
96
#define GLIU_IOD_BM5 (GLIU_MSR_BASE + 0xe5)
sys/dev/pci/glxreg.h
97
#define GLIU_IOD_BM6 (GLIU_MSR_BASE + 0xe6)
sys/dev/pci/glxreg.h
98
#define GLIU_IOD_BM7 (GLIU_MSR_BASE + 0xe7)
sys/dev/pci/glxreg.h
99
#define GLIU_IOD_BM8 (GLIU_MSR_BASE + 0xe8)