GENMASK_ULL
#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))
#define ACA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)
me = (*pos & GENMASK_ULL(33, 24)) >> 24;
pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
offset = (*pos & GENMASK_ULL(6, 0));
se = (*pos & GENMASK_ULL(14, 7)) >> 7;
sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
se = (*pos & GENMASK_ULL(19, 12)) >> 12;
sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
#define MCA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)
adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
#define IOMFB_MESSAGE_TYPE GENMASK_ULL( 3, 0)
#define IOMFB_MSG_LENGTH GENMASK_ULL(63, 32)
#define IOMFB_MSG_OFFSET GENMASK_ULL(31, 16)
#define IOMFB_MSG_CONTEXT GENMASK_ULL(11, 8)
#define IOMFB_SHMEM_DVA GENMASK_ULL(63, 16)
#define IOMFB_SHMEM_FLAG GENMASK_ULL( 7, 4)
GENMASK_ULL((__start) + (__size) - 1, (__start))
args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
#define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12)
#define MTL_GGTT_PTE_PAT_MASK GENMASK_ULL(53, 52)
#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
#define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30)
#define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21)
#define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16)
#define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)
#define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
#define PKG_PKG_TDP GENMASK_ULL(14, 0)
#define PKG_MIN_PWR GENMASK_ULL(30, 16)
#define PKG_MAX_PWR GENMASK_ULL(46, 32)
#define PKG_MAX_WIN GENMASK_ULL(54, 48)
#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
#define DRM_BUDDY_HEADER_STATE GENMASK_ULL(11, 10)
#define DRM_BUDDY_HEADER_CLEAR GENMASK_ULL(9, 9)
#define DRM_BUDDY_HEADER_UNUSED GENMASK_ULL(8, 6)
#define DRM_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0)
#define AFBC_VENDOR_AND_TYPE_MASK GENMASK_ULL(63, 52)
((u64)(GENMASK_ULL(__high, __low) + \