sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

228

unsigned int phy_inst = GET_INST(GC, xcc_inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

299

hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

300

hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

309

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

338

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

340

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

342

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

344

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

346

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

351

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

355

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

48

SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

493

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

498

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1034

soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1047

queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1072

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1111

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1113

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1119

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1121

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1137

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1140

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1141

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1163

uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1185

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1188

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1189

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1201

WREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_COMPUTE_QUEUE_RESET, 0x1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1211

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1212

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

171

WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

238

hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

241

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

248

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

277

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

279

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

281

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

283

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

285

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

290

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

294

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

372

for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

373

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

493

act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

498

if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

499

high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

54

soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

540

WREG32_FIELD15_RLC(GC, GET_INST(GC, inst), RLC_CP_SCHEDULERS, scheduler1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

557

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

561

temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

59

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

635

WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, gfx_index_val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

636

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

645

WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

909

*wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

94

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

95

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

964

soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

965

reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

971

(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

803

ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

934

amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

502

inst_id = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

46

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

49

JPEG, GET_INST(JPEG, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

73

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

75

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

78

JPEG, GET_INST(JPEG, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

87

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

89

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

146

WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

149

VCN, GET_INST(VCN, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

198

WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

201

VCN, GET_INST(VCN, inst_idx), \

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

134

i = GET_INST(GC, (ffs(inst_mask) - 1));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1237

soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1239

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1240

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1243

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1245

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1247

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1255

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1256

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1257

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1258

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1273

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1274

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1275

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1276

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1291

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1306

soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1313

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1315

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1322

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1330

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1334

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1351

RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1377

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1392

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1394

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1402

rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1416

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1420

if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1432

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1442

reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1443

reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1444

reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1445

reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1446

reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1447

reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1448

reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1449

reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1475

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1499

if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1512

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1518

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1523

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1540

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1543

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1559

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1582

rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1589

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1593

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1616

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1623

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1625

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1645

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1674

reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1685

WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1687

WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1734

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1736

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1775

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1777

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1779

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1783

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1785

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1806

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1809

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1852

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1859

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1892

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1902

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1929

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1934

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1939

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1945

mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1964

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1966

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1968

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1972

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1976

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1980

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1981

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1983

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1987

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1989

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1991

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1993

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1998

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2000

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2004

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2008

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2010

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2014

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2018

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2020

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2024

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2026

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2032

GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2038

GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2045

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2049

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2051

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2055

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2057

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2061

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2065

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2077

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2079

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2082

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2091

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2094

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2098

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2099

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2100

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2101

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2102

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2103

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2104

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2105

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2133

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2135

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2144

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2147

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2175

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2177

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2206

ring->queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2208

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2328

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2340

GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2343

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2409

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2436

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2455

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2468

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2471

WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2472

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2477

WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2478

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2496

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2501

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2506

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2511

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2565

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2574

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2587

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2596

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2609

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2617

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2623

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2626

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2630

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2633

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2638

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2646

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2649

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2652

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2656

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2659

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2673

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2682

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2685

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2694

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2697

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2701

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2703

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2708

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2796

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2801

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2810

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2815

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2986

amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

304

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

305

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3061

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

308

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3080

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3083

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3086

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3089

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3131

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3133

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3135

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3137

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3156

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3196

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3235

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3424

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3427

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3430

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3433

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3455

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3478

soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3480

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3488

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3518

reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

353

dev_inst = GET_INST(GC, i);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3551

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3552

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

426

scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4413

GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4422

GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4443

GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4479

GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4484

GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4501

GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4520

data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4536

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4662

GET_INST(GC, xcc_id)));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4681

GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4689

RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4697

GET_INST(GC, xcc_id)));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4886

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4893

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4894

data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4961

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4964

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

514

WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

515

clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

516

((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

713

WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

718

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

723

return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

730

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

738

*(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

784

soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

792

xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

817

WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

101

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

104

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

108

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

111

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

115

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

118

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

135

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

136

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

137

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

141

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

154

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

159

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

165

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

167

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

171

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

173

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

176

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

179

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

186

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

187

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

188

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

189

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, 0xFFFFFF);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

190

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

191

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

204

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

218

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

230

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

239

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

241

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

244

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

256

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

267

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

278

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

286

WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

297

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

300

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

304

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

307

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

311

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

313

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

346

tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

380

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

382

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

385

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

388

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

39

return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

392

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

410

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

412

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

456

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

460

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

466

WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

470

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

472

WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

473

WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

494

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

52

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

525

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

553

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

556

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

559

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

561

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

563

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

565

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

567

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

57

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

570

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

601

xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

603

RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

94

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

97

WREG32_SOC15(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

276

1 << vmid, GET_INST(GC, 0));

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

264

1 << vmid, GET_INST(GC, 0));

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

338

1 << vmid, GET_INST(GC, 0));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

889

tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

891

tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

902

WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

904

WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

917

tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

919

tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

932

WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

934

WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1122

int jpeg_inst = GET_INST(JPEG, ring->me);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1216

jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1298

NULL, 0, GET_INST(VCN, jpeg_inst),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1323

GET_INST(VCN, jpeg_inst));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

173

jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

276

jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

392

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

397

jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

412

VCN, GET_INST(VCN, i),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

498

jpeg_inst = GET_INST(JPEG, inst_idx);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

523

jpeg_inst = GET_INST(JPEG, inst_idx);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

545

int jpeg_inst = GET_INST(JPEG, inst);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

575

int jpeg_inst = GET_INST(JPEG, ring->me);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

637

int jpeg_inst = GET_INST(JPEG, inst);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

680

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

698

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

724

WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

978

ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

996

ret &= (SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

170

jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

271

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

275

jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

285

WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

368

int jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

389

int jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

405

int jpeg_inst = GET_INST(JPEG, ring->me);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

474

jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

613

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

631

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

650

WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

667

ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

687

ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

821

int jpeg_inst = GET_INST(JPEG, ring->me);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

917

jpeg_inst = GET_INST(JPEG, i);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

79

dev_inst = GET_INST(SDMA0, instance);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

119

u32 dev_inst = GET_INST(SDMA0, instance);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1743

return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2040

data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2045

data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2187

dev_inst = GET_INST(SDMA0, i);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2463

uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2501

uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1025

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1198

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1364

vcn_inst = GET_INST(VCN, inst_idx);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1404

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1507

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1527

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1594

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1610

vcn_inst = GET_INST(VCN, ring->me);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1619

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1672

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1691

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1711

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1738

if (RREG32_SOC15(VCN, GET_INST(VCN, i),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1920

NULL, 0, GET_INST(VCN, vcn_inst),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1945

GET_INST(VCN, vcn_inst));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

199

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

299

vcn_inst = GET_INST(VCN, inst_idx);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

345

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

462

vcn_inst = GET_INST(VCN, inst_idx);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

653

vcn_inst = GET_INST(VCN, inst_idx);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

800

vcn_inst = GET_INST(VCN, inst_idx);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

854

vcn_inst = GET_INST(VCN, inst_idx);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1140

vcn_inst = GET_INST(VCN, inst_idx);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1178

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1258

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1278

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1299

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1315

vcn_inst = GET_INST(VCN, ring->me);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1374

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1392

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1410

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1438

if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

177

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

278

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

316

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

430

vcn_inst = GET_INST(VCN, inst);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

627

vcn_inst = GET_INST(VCN, vinst->inst);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

678

vcn_inst = GET_INST(VCN, inst_idx);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

817

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

992

vcn_inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

707

mapped_xcc = GET_INST(GC, xcc);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

381

xcc_id = GET_INST(GC, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

735

inst = GET_INST(VCN, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

759

inst = GET_INST(GC, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

814

xcc_id = GET_INST(GC, i);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

822

inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

845

gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

888

inst = GET_INST(VCN, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

904

inst = GET_INST(GC, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1287

xcc_id = GET_INST(GC, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2678

inst = GET_INST(VCN, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2706

inst = GET_INST(GC, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2797

xcc_id = GET_INST(GC, i);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2805

inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2832

version) >> GET_INST(GC, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2904

inst = GET_INST(VCN, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2922

inst = GET_INST(GC, k);