Symbol: GENMASK
sys/dev/ic/qwxreg.h
10054
#define HTC_HDR_ENDPOINTID GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10055
#define HTC_HDR_FLAGS GENMASK(15, 8)
sys/dev/ic/qwxreg.h
10056
#define HTC_HDR_PAYLOADLEN GENMASK(31, 16)
sys/dev/ic/qwxreg.h
10057
#define HTC_HDR_CONTROLBYTES0 GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10058
#define HTC_HDR_CONTROLBYTES1 GENMASK(15, 8)
sys/dev/ic/qwxreg.h
10059
#define HTC_HDR_RESERVED GENMASK(31, 16)
sys/dev/ic/qwxreg.h
10061
#define HTC_SVC_MSG_SERVICE_ID GENMASK(31, 16)
sys/dev/ic/qwxreg.h
10062
#define HTC_SVC_MSG_CONNECTIONFLAGS GENMASK(15, 0)
sys/dev/ic/qwxreg.h
10063
#define HTC_SVC_MSG_SERVICEMETALENGTH GENMASK(23, 16)
sys/dev/ic/qwxreg.h
10064
#define HTC_READY_MSG_CREDITCOUNT GENMASK(31, 16)
sys/dev/ic/qwxreg.h
10065
#define HTC_READY_MSG_CREDITSIZE GENMASK(15, 0)
sys/dev/ic/qwxreg.h
10066
#define HTC_READY_MSG_MAXENDPOINTS GENMASK(23, 16)
sys/dev/ic/qwxreg.h
10068
#define HTC_READY_EX_MSG_HTCVERSION GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10069
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE GENMASK(15, 8)
sys/dev/ic/qwxreg.h
10071
#define HTC_SVC_RESP_MSG_SERVICEID GENMASK(31, 16)
sys/dev/ic/qwxreg.h
10072
#define HTC_SVC_RESP_MSG_STATUS GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10073
#define HTC_SVC_RESP_MSG_ENDPOINTID GENMASK(15, 8)
sys/dev/ic/qwxreg.h
10074
#define HTC_SVC_RESP_MSG_MAXMSGSIZE GENMASK(31, 16)
sys/dev/ic/qwxreg.h
10075
#define HTC_SVC_RESP_MSG_SERVICEMETALENGTH GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10077
#define HTC_MSG_MESSAGEID GENMASK(15, 0)
sys/dev/ic/qwxreg.h
10078
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS GENMASK(31, 0)
sys/dev/ic/qwxreg.h
10079
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10080
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0 GENMASK(15, 8)
sys/dev/ic/qwxreg.h
10081
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1 GENMASK(23, 16)
sys/dev/ic/qwxreg.h
10082
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2 GENMASK(31, 24)
sys/dev/ic/qwxreg.h
10116
#define ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0)
sys/dev/ic/qwxreg.h
10117
#define ATH11K_HTC_CONN_FLAGS_RECV_ALLOC GENMASK(15, 8)
sys/dev/ic/qwxreg.h
10383
#define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
sys/dev/ic/qwxreg.h
10384
#define RX_DESC_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)
sys/dev/ic/qwxreg.h
10502
#define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE GENMASK(12, 10)
sys/dev/ic/qwxreg.h
10726
#define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER GENMASK(13, 10)
sys/dev/ic/qwxreg.h
10732
#define RX_MPDU_START_INFO1_MPDU_SEQ_NUM GENMASK(31, 20)
sys/dev/ic/qwxreg.h
10736
#define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)
sys/dev/ic/qwxreg.h
10737
#define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6)
sys/dev/ic/qwxreg.h
10740
#define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10)
sys/dev/ic/qwxreg.h
10741
#define RX_MPDU_START_INFO2_TID GENMASK(17, 14)
sys/dev/ic/qwxreg.h
10742
#define RX_MPDU_START_INFO2_TID_WCN6855 GENMASK(18, 15)
sys/dev/ic/qwxreg.h
10744
#define RX_MPDU_START_INFO3_REO_DEST_IND GENMASK(4, 0)
sys/dev/ic/qwxreg.h
10749
#define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL GENMASK(12, 11)
sys/dev/ic/qwxreg.h
10750
#define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL GENMASK(14, 13)
sys/dev/ic/qwxreg.h
10752
#define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10753
#define RX_MPDU_START_INFO4_RECV_QUEUE_NUM GENMASK(23, 8)
sys/dev/ic/qwxreg.h
10757
#define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10760
#define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10)
sys/dev/ic/qwxreg.h
10765
#define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16)
sys/dev/ic/qwxreg.h
10769
#define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0)
sys/dev/ic/qwxreg.h
10815
#define RX_MPDU_START_INFO7_REO_DEST_IND GENMASK(4, 0)
sys/dev/ic/qwxreg.h
10816
#define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB GENMASK(6, 5)
sys/dev/ic/qwxreg.h
10821
#define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL GENMASK(12, 11)
sys/dev/ic/qwxreg.h
10822
#define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL GENMASK(14, 13)
sys/dev/ic/qwxreg.h
10824
#define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10825
#define RX_MPDU_START_INFO8_RECV_QUEUE_NUM GENMASK(23, 8)
sys/dev/ic/qwxreg.h
10831
#define RX_MPDU_START_INFO9_ENC_TYPE GENMASK(5, 2)
sys/dev/ic/qwxreg.h
10832
#define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH GENMASK(7, 6)
sys/dev/ic/qwxreg.h
10833
#define RX_MPDU_START_INFO9_MESH_STA GENMASK(9, 8)
sys/dev/ic/qwxreg.h
10835
#define RX_MPDU_START_INFO9_BSSID_NUM GENMASK(14, 11)
sys/dev/ic/qwxreg.h
10836
#define RX_MPDU_START_INFO9_TID GENMASK(18, 15)
sys/dev/ic/qwxreg.h
10838
#define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR GENMASK(1, 0)
sys/dev/ic/qwxreg.h
10839
#define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID GENMASK(8, 2)
sys/dev/ic/qwxreg.h
10856
#define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER GENMASK(13, 10)
sys/dev/ic/qwxreg.h
10862
#define RX_MPDU_START_INFO11_MPDU_SEQ_NUM GENMASK(31, 20)
sys/dev/ic/qwxreg.h
10864
#define RX_MPDU_START_INFO12_KEY_ID GENMASK(7, 0)
sys/dev/ic/qwxreg.h
10867
#define RX_MPDU_START_INFO12_DECAP_TYPE GENMASK(11, 10)
sys/dev/ic/qwxreg.h
10872
#define RX_MPDU_START_INFO12_PRE_DELIM_COUNT GENMASK(27, 16)
sys/dev/ic/qwxreg.h
10877
#define RX_MPDU_START_INFO13_MPDU_LEN GENMASK(13, 0)
sys/dev/ic/qwxreg.h
11144
#define RX_MSDU_START_INFO1_MSDU_LENGTH GENMASK(13, 0)
sys/dev/ic/qwxreg.h
11147
#define RX_MSDU_START_INFO1_L3_OFFSET GENMASK(22, 16)
sys/dev/ic/qwxreg.h
11149
#define RX_MSDU_START_INFO1_L4_OFFSET GENMASK(31, 24)
sys/dev/ic/qwxreg.h
11151
#define RX_MSDU_START_INFO2_MSDU_NUMBER GENMASK(7, 0)
sys/dev/ic/qwxreg.h
11152
#define RX_MSDU_START_INFO2_DECAP_TYPE GENMASK(9, 8)
sys/dev/ic/qwxreg.h
11160
#define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH GENMASK(18, 17)
sys/dev/ic/qwxreg.h
11166
#define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR GENMASK(31, 24)
sys/dev/ic/qwxreg.h
11167
#define RX_MSDU_START_INFO2_DECAP_FORMAT GENMASK(9, 8)
sys/dev/ic/qwxreg.h
11169
#define RX_MSDU_START_INFO3_USER_RSSI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
11170
#define RX_MSDU_START_INFO3_PKT_TYPE GENMASK(11, 8)
sys/dev/ic/qwxreg.h
11172
#define RX_MSDU_START_INFO3_SGI GENMASK(14, 13)
sys/dev/ic/qwxreg.h
11173
#define RX_MSDU_START_INFO3_RATE_MCS GENMASK(18, 15)
sys/dev/ic/qwxreg.h
11174
#define RX_MSDU_START_INFO3_RECV_BW GENMASK(20, 19)
sys/dev/ic/qwxreg.h
11175
#define RX_MSDU_START_INFO3_RECEPTION_TYPE GENMASK(23, 21)
sys/dev/ic/qwxreg.h
11176
#define RX_MSDU_START_INFO3_MIMO_SS_BITMAP GENMASK(31, 24)
sys/dev/ic/qwxreg.h
11391
#define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
sys/dev/ic/qwxreg.h
11392
#define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)
sys/dev/ic/qwxreg.h
11394
#define RX_MSDU_END_INFO1_KEY_ID GENMASK(7, 0)
sys/dev/ic/qwxreg.h
11395
#define RX_MSDU_END_INFO1_CCE_SUPER_RULE GENMASK(13, 8)
sys/dev/ic/qwxreg.h
11398
#define RX_MSDU_END_INFO1_EXT_WAPI_PN GENMASK(31, 16)
sys/dev/ic/qwxreg.h
11400
#define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN GENMASK(13, 0)
sys/dev/ic/qwxreg.h
11415
#define RX_MSDU_END_INFO2_L3_HDR_PADDING GENMASK(27, 26)
sys/dev/ic/qwxreg.h
11417
#define RX_MSDU_END_INFO3_TCP_FLAG GENMASK(8, 0)
sys/dev/ic/qwxreg.h
11420
#define RX_MSDU_END_INFO4_DA_OFFSET GENMASK(5, 0)
sys/dev/ic/qwxreg.h
11421
#define RX_MSDU_END_INFO4_SA_OFFSET GENMASK(11, 6)
sys/dev/ic/qwxreg.h
11424
#define RX_MSDU_END_INFO4_L3_TYPE GENMASK(31, 16)
sys/dev/ic/qwxreg.h
11427
#define RX_MSDU_END_INFO5_REO_DEST_IND GENMASK(5, 1)
sys/dev/ic/qwxreg.h
11428
#define RX_MSDU_END_INFO5_FLOW_IDX GENMASK(25, 6)
sys/dev/ic/qwxreg.h
11478
#define RX_MSDU_END_MPDU_LENGTH_INFO GENMASK(13, 0)
sys/dev/ic/qwxreg.h
11480
#define RX_MSDU_END_INFO2_DA_OFFSET GENMASK(5, 0)
sys/dev/ic/qwxreg.h
11481
#define RX_MSDU_END_INFO2_SA_OFFSET GENMASK(11, 6)
sys/dev/ic/qwxreg.h
11484
#define RX_MSDU_END_INFO2_L3_TYPE GENMASK(31, 16)
sys/dev/ic/qwxreg.h
11496
#define RX_MSDU_END_INFO4_L3_HDR_PADDING GENMASK(11, 10)
sys/dev/ic/qwxreg.h
11500
#define RX_MSDU_END_INFO6_AGGR_COUNT GENMASK(7, 0)
sys/dev/ic/qwxreg.h
11709
#define RX_MPDU_END_INFO1_RXDMA0_DEST_RING GENMASK(22, 21)
sys/dev/ic/qwxreg.h
11710
#define RX_MPDU_END_INFO1_RXDMA1_DEST_RING GENMASK(24, 23)
sys/dev/ic/qwxreg.h
11711
#define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE GENMASK(27, 25)
sys/dev/ic/qwxreg.h
11886
#define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
sys/dev/ic/qwxreg.h
11887
#define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
sys/dev/ic/qwxreg.h
11891
#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
sys/dev/ic/qwxreg.h
11898
#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9)
sys/dev/ic/qwxreg.h
11899
#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
sys/dev/ic/qwxreg.h
11900
#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
sys/dev/ic/qwxreg.h
11902
#define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24)
sys/dev/ic/qwxreg.h
11903
#define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0)
sys/dev/ic/qwxreg.h
11922
#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
sys/dev/ic/qwxreg.h
12072
#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwxreg.h
12073
#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
sys/dev/ic/qwxreg.h
12074
#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
sys/dev/ic/qwxreg.h
12075
#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
sys/dev/ic/qwxreg.h
12077
#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
sys/dev/ic/qwxreg.h
12078
#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
sys/dev/ic/qwxreg.h
12084
#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
sys/dev/ic/qwxreg.h
12086
#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
sys/dev/ic/qwxreg.h
12088
#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
sys/dev/ic/qwxreg.h
12145
#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwxreg.h
12147
#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9)
sys/dev/ic/qwxreg.h
12148
#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
sys/dev/ic/qwxreg.h
12257
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwxreg.h
12258
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
sys/dev/ic/qwxreg.h
12259
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
sys/dev/ic/qwxreg.h
12263
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
sys/dev/ic/qwxreg.h
12585
#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwxreg.h
12586
#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
sys/dev/ic/qwxreg.h
12591
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3)
sys/dev/ic/qwxreg.h
12629
#define HTT_T2H_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwxreg.h
12630
#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
sys/dev/ic/qwxreg.h
12631
#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
sys/dev/ic/qwxreg.h
12637
#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
sys/dev/ic/qwxreg.h
12638
#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
sys/dev/ic/qwxreg.h
12639
#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
sys/dev/ic/qwxreg.h
12640
#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
sys/dev/ic/qwxreg.h
12641
#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
sys/dev/ic/qwxreg.h
12673
#define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
sys/dev/ic/qwxreg.h
12674
#define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
sys/dev/ic/qwxreg.h
12675
#define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
sys/dev/ic/qwxreg.h
12677
#define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
sys/dev/ic/qwxreg.h
12678
#define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
sys/dev/ic/qwxreg.h
12764
#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
sys/dev/ic/qwxreg.h
12765
#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
sys/dev/ic/qwxreg.h
12780
#define HTT_TLV_TAG GENMASK(11, 0)
sys/dev/ic/qwxreg.h
12781
#define HTT_TLV_LEN GENMASK(23, 12)
sys/dev/ic/qwxreg.h
12793
#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
sys/dev/ic/qwxreg.h
12794
#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
sys/dev/ic/qwxreg.h
12796
#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
sys/dev/ic/qwxreg.h
128
#define WMI_TLV_LEN GENMASK(15, 0)
sys/dev/ic/qwxreg.h
12823
#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
sys/dev/ic/qwxreg.h
12824
#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
sys/dev/ic/qwxreg.h
12827
#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
sys/dev/ic/qwxreg.h
12829
#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
sys/dev/ic/qwxreg.h
12832
#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
sys/dev/ic/qwxreg.h
12833
#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
sys/dev/ic/qwxreg.h
12834
#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
sys/dev/ic/qwxreg.h
12835
#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
sys/dev/ic/qwxreg.h
12836
#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
sys/dev/ic/qwxreg.h
12837
#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
sys/dev/ic/qwxreg.h
12854
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
sys/dev/ic/qwxreg.h
12857
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
sys/dev/ic/qwxreg.h
12858
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
sys/dev/ic/qwxreg.h
12859
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
sys/dev/ic/qwxreg.h
12860
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
sys/dev/ic/qwxreg.h
12861
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
sys/dev/ic/qwxreg.h
12862
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
sys/dev/ic/qwxreg.h
12881
#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
sys/dev/ic/qwxreg.h
12883
#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
sys/dev/ic/qwxreg.h
12884
#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
sys/dev/ic/qwxreg.h
12886
#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
sys/dev/ic/qwxreg.h
129
#define WMI_TLV_TAG GENMASK(31, 16)
sys/dev/ic/qwxreg.h
12917
#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
sys/dev/ic/qwxreg.h
12918
#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
sys/dev/ic/qwxreg.h
12920
#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
sys/dev/ic/qwxreg.h
12940
#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
sys/dev/ic/qwxreg.h
12941
#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
sys/dev/ic/qwxreg.h
12942
#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
sys/dev/ic/qwxreg.h
132
#define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
sys/dev/ic/qwxreg.h
13240
#define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
sys/dev/ic/qwxreg.h
13249
#define HTT_MAC_ADDR_L32_0 GENMASK(7, 0)
sys/dev/ic/qwxreg.h
13250
#define HTT_MAC_ADDR_L32_1 GENMASK(15, 8)
sys/dev/ic/qwxreg.h
13251
#define HTT_MAC_ADDR_L32_2 GENMASK(23, 16)
sys/dev/ic/qwxreg.h
13252
#define HTT_MAC_ADDR_L32_3 GENMASK(31, 24)
sys/dev/ic/qwxreg.h
13253
#define HTT_MAC_ADDR_H16_0 GENMASK(7, 0)
sys/dev/ic/qwxreg.h
13254
#define HTT_MAC_ADDR_H16_1 GENMASK(15, 8)
sys/dev/ic/qwxreg.h
2559
#define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1)
sys/dev/ic/qwxreg.h
3353
#define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0)
sys/dev/ic/qwxreg.h
3540
#define WMI_CHAN_INFO_MODE GENMASK(5, 0)
sys/dev/ic/qwxreg.h
3555
#define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0)
sys/dev/ic/qwxreg.h
3556
#define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8)
sys/dev/ic/qwxreg.h
3557
#define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16)
sys/dev/ic/qwxreg.h
3558
#define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24)
sys/dev/ic/qwxreg.h
3560
#define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0)
sys/dev/ic/qwxreg.h
3561
#define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8)
sys/dev/ic/qwxreg.h
3861
#define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0)
sys/dev/ic/qwxreg.h
3862
#define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8)
sys/dev/ic/qwxreg.h
3863
#define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20)
sys/dev/ic/qwxreg.h
3864
#define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
3866
#define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0)
sys/dev/ic/qwxreg.h
3867
#define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8)
sys/dev/ic/qwxreg.h
3868
#define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15)
sys/dev/ic/qwxreg.h
3870
#define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21)
sys/dev/ic/qwxreg.h
5672
#define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0)
sys/dev/ic/qwxreg.h
5673
#define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16)
sys/dev/ic/qwxreg.h
5675
#define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7307
#define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
sys/dev/ic/qwxreg.h
7308
#define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7309
#define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7315
#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16)
sys/dev/ic/qwxreg.h
7316
#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
sys/dev/ic/qwxreg.h
7317
#define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)
sys/dev/ic/qwxreg.h
7319
#define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7321
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)
sys/dev/ic/qwxreg.h
7322
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)
sys/dev/ic/qwxreg.h
7323
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)
sys/dev/ic/qwxreg.h
7324
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6)
sys/dev/ic/qwxreg.h
7325
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9)
sys/dev/ic/qwxreg.h
7326
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12)
sys/dev/ic/qwxreg.h
7327
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15)
sys/dev/ic/qwxreg.h
7328
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18)
sys/dev/ic/qwxreg.h
7329
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21)
sys/dev/ic/qwxreg.h
7332
#define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
sys/dev/ic/qwxreg.h
7333
#define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7334
#define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8)
sys/dev/ic/qwxreg.h
7335
#define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7340
#define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16)
sys/dev/ic/qwxreg.h
7341
#define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
sys/dev/ic/qwxreg.h
7343
#define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7344
#define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23)
sys/dev/ic/qwxreg.h
7347
#define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17)
sys/dev/ic/qwxreg.h
7350
#define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
sys/dev/ic/qwxreg.h
7358
#define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2)
sys/dev/ic/qwxreg.h
7359
#define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)
sys/dev/ic/qwxreg.h
7360
#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7361
#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8)
sys/dev/ic/qwxreg.h
7363
#define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8)
sys/dev/ic/qwxreg.h
7364
#define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8)
sys/dev/ic/qwxreg.h
7388
#define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
sys/dev/ic/qwxreg.h
7390
#define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
sys/dev/ic/qwxreg.h
7391
#define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)
sys/dev/ic/qwxreg.h
7392
#define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)
sys/dev/ic/qwxreg.h
7853
#define HAL_TLV_HDR_TAG GENMASK(9, 1)
sys/dev/ic/qwxreg.h
7854
#define HAL_TLV_HDR_LEN GENMASK(25, 10)
sys/dev/ic/qwxreg.h
7855
#define HAL_TLV_USR_ID GENMASK(31, 26)
sys/dev/ic/qwxreg.h
7954
#define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3)
sys/dev/ic/qwxreg.h
7955
#define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17)
sys/dev/ic/qwxreg.h
8056
#define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
8058
#define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9)
sys/dev/ic/qwxreg.h
8059
#define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11)
sys/dev/ic/qwxreg.h
8060
#define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16)
sys/dev/ic/qwxreg.h
8063
#define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1)
sys/dev/ic/qwxreg.h
8064
#define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5)
sys/dev/ic/qwxreg.h
8066
#define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
8067
#define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
8164
#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
8165
#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8)
sys/dev/ic/qwxreg.h
8166
#define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22)
sys/dev/ic/qwxreg.h
8169
#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)
sys/dev/ic/qwxreg.h
8170
#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2)
sys/dev/ic/qwxreg.h
8240
#define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)
sys/dev/ic/qwxreg.h
8241
#define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2)
sys/dev/ic/qwxreg.h
8242
#define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7)
sys/dev/ic/qwxreg.h
8244
#define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12)
sys/dev/ic/qwxreg.h
8247
#define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)
sys/dev/ic/qwxreg.h
8248
#define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
8249
#define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
8259
#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)
sys/dev/ic/qwxreg.h
8306
#define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17)
sys/dev/ic/qwxreg.h
8309
#define HAL_REO_CMD_UPD1_AC GENMASK(22, 21)
sys/dev/ic/qwxreg.h
8322
#define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11)
sys/dev/ic/qwxreg.h
8326
#define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8)
sys/dev/ic/qwxreg.h
8345
#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
8386
#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
8388
#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9)
sys/dev/ic/qwxreg.h
8397
#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
8400
#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10)
sys/dev/ic/qwxreg.h
8414
#define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2)
sys/dev/ic/qwxreg.h
8415
#define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4)
sys/dev/ic/qwxreg.h
8418
#define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12)
sys/dev/ic/qwxreg.h
8419
#define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14)
sys/dev/ic/qwxreg.h
8420
#define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16)
sys/dev/ic/qwxreg.h
8422
#define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0)
sys/dev/ic/qwxreg.h
8429
#define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23)
sys/dev/ic/qwxreg.h
8431
#define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0)
sys/dev/ic/qwxreg.h
8435
#define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22)
sys/dev/ic/qwxreg.h
8436
#define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26)
sys/dev/ic/qwxreg.h
8438
#define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0)
sys/dev/ic/qwxreg.h
8439
#define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6)
sys/dev/ic/qwxreg.h
8440
#define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26)
sys/dev/ic/qwxreg.h
8441
#define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30)
sys/dev/ic/qwxreg.h
8443
#define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
8444
#define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
8665
#define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
8666
#define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8)
sys/dev/ic/qwxreg.h
8671
#define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
8672
#define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
8713
#define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0)
sys/dev/ic/qwxreg.h
8715
#define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5)
sys/dev/ic/qwxreg.h
8716
#define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8)
sys/dev/ic/qwxreg.h
8718
#define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0)
sys/dev/ic/qwxreg.h
8720
#define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
8721
#define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
8756
#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
8761
#define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16)
sys/dev/ic/qwxreg.h
8763
#define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)
sys/dev/ic/qwxreg.h
8765
#define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
8853
#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
8854
#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
8906
#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16)
sys/dev/ic/qwxreg.h
8908
#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)
sys/dev/ic/qwxreg.h
8909
#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
8985
#define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1)
sys/dev/ic/qwxreg.h
8986
#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3)
sys/dev/ic/qwxreg.h
8989
#define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9)
sys/dev/ic/qwxreg.h
8990
#define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11)
sys/dev/ic/qwxreg.h
8992
#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16)
sys/dev/ic/qwxreg.h
9093
#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)
sys/dev/ic/qwxreg.h
9094
#define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3)
sys/dev/ic/qwxreg.h
9095
#define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6)
sys/dev/ic/qwxreg.h
9096
#define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)
sys/dev/ic/qwxreg.h
9097
#define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13)
sys/dev/ic/qwxreg.h
9098
#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
sys/dev/ic/qwxreg.h
9099
#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
sys/dev/ic/qwxreg.h
9100
#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24)
sys/dev/ic/qwxreg.h
9101
#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26)
sys/dev/ic/qwxreg.h
9104
#define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
sys/dev/ic/qwxreg.h
9105
#define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24)
sys/dev/ic/qwxreg.h
9107
#define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
9113
#define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)
sys/dev/ic/qwxreg.h
9115
#define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0)
sys/dev/ic/qwxreg.h
9116
#define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16)
sys/dev/ic/qwxreg.h
9117
#define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20)
sys/dev/ic/qwxreg.h
9118
#define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
9120
#define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9)
sys/dev/ic/qwxreg.h
9121
#define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13)
sys/dev/ic/qwxreg.h
9347
#define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
sys/dev/ic/qwxreg.h
9348
#define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4)
sys/dev/ic/qwxreg.h
9349
#define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8)
sys/dev/ic/qwxreg.h
9364
#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)
sys/dev/ic/qwxreg.h
9398
#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)
sys/dev/ic/qwxreg.h
9401
#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1)
sys/dev/ic/qwxreg.h
9404
#define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5)
sys/dev/ic/qwxreg.h
9409
#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11)
sys/dev/ic/qwxreg.h
9414
#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23)
sys/dev/ic/qwxreg.h
9418
#define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1)
sys/dev/ic/qwxreg.h
9419
#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13)
sys/dev/ic/qwxreg.h
9424
#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)
sys/dev/ic/qwxreg.h
9427
#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4)
sys/dev/ic/qwxreg.h
9428
#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10)
sys/dev/ic/qwxreg.h
9429
#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16)
sys/dev/ic/qwxreg.h
9431
#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)
sys/dev/ic/qwxreg.h
9432
#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24)
sys/dev/ic/qwxreg.h
9434
#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)
sys/dev/ic/qwxreg.h
9435
#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12)
sys/dev/ic/qwxreg.h
9436
#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16)
sys/dev/ic/qwxreg.h
9526
#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwxreg.h
9551
#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)
sys/dev/ic/qwxreg.h
9553
#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17)
sys/dev/ic/qwxreg.h
9556
#define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21)
sys/dev/ic/qwxreg.h
9567
#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0)
sys/dev/ic/qwxreg.h
9568
#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8)
sys/dev/ic/qwxreg.h
9570
#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11)
sys/dev/ic/qwxreg.h
9585
#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1)
sys/dev/ic/qwxreg.h
9600
#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)
sys/dev/ic/qwxreg.h
9601
#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16)
sys/dev/ic/qwxreg.h
9602
#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26)
sys/dev/ic/qwxreg.h
9635
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)
sys/dev/ic/qwxreg.h
9636
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12)
sys/dev/ic/qwxreg.h
9638
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)
sys/dev/ic/qwxreg.h
9639
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7)
sys/dev/ic/qwxreg.h
9641
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4)
sys/dev/ic/qwxreg.h
9642
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10)
sys/dev/ic/qwxreg.h
9643
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16)
sys/dev/ic/qwxreg.h
9645
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)
sys/dev/ic/qwxreg.h
9646
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24)
sys/dev/ic/qwxreg.h
9648
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)
sys/dev/ic/qwxreg.h
9649
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12)
sys/dev/ic/qwxreg.h
9650
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16)
sys/dev/ic/qwxreg.h
9652
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
9743
#define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28)
sys/dev/ic/qwxreg.h
9746
#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1)
sys/dev/ic/qwxreg.h
9747
#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)
sys/dev/ic/qwxreg.h
9777
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1)
sys/dev/ic/qwxreg.h
9779
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9)
sys/dev/ic/qwxreg.h
9780
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12)
sys/dev/ic/qwxreg.h
9781
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16)
sys/dev/ic/qwxreg.h
9782
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18)
sys/dev/ic/qwxreg.h
9879
#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)
sys/dev/ic/qwxreg.h
9880
#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16)
sys/dev/ic/qwxreg.h
9919
#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)
sys/dev/ic/qwxreg.h
9920
#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)
sys/dev/ic/qwxreg.h
9921
#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)
sys/dev/ic/qwxreg.h
9922
#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)
sys/dev/ic/qwxreg.h
9923
#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)
sys/dev/ic/qwxvar.h
1000
#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
sys/dev/ic/qwxvar.h
512
#define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
sys/dev/ic/qwxvar.h
513
#define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
sys/dev/ic/qwxvar.h
992
#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
sys/dev/ic/qwxvar.h
993
#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
sys/dev/ic/qwxvar.h
998
#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
sys/dev/ic/qwxvar.h
999
#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
sys/dev/ic/qwzreg.h
10000
#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8)
sys/dev/ic/qwzreg.h
10002
#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11)
sys/dev/ic/qwzreg.h
10017
#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1)
sys/dev/ic/qwzreg.h
10032
#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)
sys/dev/ic/qwzreg.h
10033
#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16)
sys/dev/ic/qwzreg.h
10034
#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26)
sys/dev/ic/qwzreg.h
10067
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)
sys/dev/ic/qwzreg.h
10068
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12)
sys/dev/ic/qwzreg.h
10070
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)
sys/dev/ic/qwzreg.h
10071
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7)
sys/dev/ic/qwzreg.h
10073
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4)
sys/dev/ic/qwzreg.h
10074
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10)
sys/dev/ic/qwzreg.h
10075
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10077
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)
sys/dev/ic/qwzreg.h
10078
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24)
sys/dev/ic/qwzreg.h
10080
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)
sys/dev/ic/qwzreg.h
10081
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12)
sys/dev/ic/qwzreg.h
10082
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10084
#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
10175
#define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
10178
#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1)
sys/dev/ic/qwzreg.h
10179
#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)
sys/dev/ic/qwzreg.h
10209
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1)
sys/dev/ic/qwzreg.h
10211
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9)
sys/dev/ic/qwzreg.h
10212
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12)
sys/dev/ic/qwzreg.h
10213
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16)
sys/dev/ic/qwzreg.h
10214
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18)
sys/dev/ic/qwzreg.h
10311
#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)
sys/dev/ic/qwzreg.h
10312
#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10351
#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)
sys/dev/ic/qwzreg.h
10352
#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)
sys/dev/ic/qwzreg.h
10353
#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)
sys/dev/ic/qwzreg.h
10354
#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)
sys/dev/ic/qwzreg.h
10355
#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)
sys/dev/ic/qwzreg.h
10542
#define HTC_HDR_ENDPOINTID GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10543
#define HTC_HDR_FLAGS GENMASK(15, 8)
sys/dev/ic/qwzreg.h
10544
#define HTC_HDR_PAYLOADLEN GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10545
#define HTC_HDR_CONTROLBYTES0 GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10546
#define HTC_HDR_CONTROLBYTES1 GENMASK(15, 8)
sys/dev/ic/qwzreg.h
10547
#define HTC_HDR_RESERVED GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10549
#define HTC_SVC_MSG_SERVICE_ID GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10550
#define HTC_SVC_MSG_CONNECTIONFLAGS GENMASK(15, 0)
sys/dev/ic/qwzreg.h
10551
#define HTC_SVC_MSG_SERVICEMETALENGTH GENMASK(23, 16)
sys/dev/ic/qwzreg.h
10552
#define HTC_READY_MSG_CREDITCOUNT GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10553
#define HTC_READY_MSG_CREDITSIZE GENMASK(15, 0)
sys/dev/ic/qwzreg.h
10554
#define HTC_READY_MSG_MAXENDPOINTS GENMASK(23, 16)
sys/dev/ic/qwzreg.h
10556
#define HTC_READY_EX_MSG_HTCVERSION GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10557
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE GENMASK(15, 8)
sys/dev/ic/qwzreg.h
10559
#define HTC_SVC_RESP_MSG_SERVICEID GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10560
#define HTC_SVC_RESP_MSG_STATUS GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10561
#define HTC_SVC_RESP_MSG_ENDPOINTID GENMASK(15, 8)
sys/dev/ic/qwzreg.h
10562
#define HTC_SVC_RESP_MSG_MAXMSGSIZE GENMASK(31, 16)
sys/dev/ic/qwzreg.h
10563
#define HTC_SVC_RESP_MSG_SERVICEMETALENGTH GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10565
#define HTC_MSG_MESSAGEID GENMASK(15, 0)
sys/dev/ic/qwzreg.h
10566
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS GENMASK(31, 0)
sys/dev/ic/qwzreg.h
10567
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10568
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0 GENMASK(15, 8)
sys/dev/ic/qwzreg.h
10569
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1 GENMASK(23, 16)
sys/dev/ic/qwzreg.h
10570
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2 GENMASK(31, 24)
sys/dev/ic/qwzreg.h
10604
#define ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0)
sys/dev/ic/qwzreg.h
10605
#define ATH12K_HTC_CONN_FLAGS_RECV_ALLOC GENMASK(15, 8)
sys/dev/ic/qwzreg.h
10886
#define RX_MPDU_START_INFO0_REO_DEST_IND GENMASK(4, 0)
sys/dev/ic/qwzreg.h
10887
#define RX_MPDU_START_INFO0_LMAC_PEER_ID_MSB GENMASK(6, 5)
sys/dev/ic/qwzreg.h
10892
#define RX_MPDU_START_INFO0_RXDMA0_SRC_RING_SEL GENMASK(13, 11)
sys/dev/ic/qwzreg.h
10893
#define RX_MPDU_START_INFO0_RXDMA0_DST_RING_SEL GENMASK(16, 14)
sys/dev/ic/qwzreg.h
10900
#define RX_MPDU_START_INFO1_REO_QUEUE_DESC_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10901
#define RX_MPDU_START_INFO1_RECV_QUEUE_NUM GENMASK(23, 8)
sys/dev/ic/qwzreg.h
10907
#define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)
sys/dev/ic/qwzreg.h
10908
#define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6)
sys/dev/ic/qwzreg.h
10909
#define RX_MPDU_START_INFO2_MESH_STA GENMASK(9, 8)
sys/dev/ic/qwzreg.h
10911
#define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(14, 11)
sys/dev/ic/qwzreg.h
10912
#define RX_MPDU_START_INFO2_TID GENMASK(18, 15)
sys/dev/ic/qwzreg.h
10914
#define RX_MPDU_START_INFO3_RXPCU_MPDU_FLTR GENMASK(1, 0)
sys/dev/ic/qwzreg.h
10915
#define RX_MPDU_START_INFO3_SW_FRAME_GRP_ID GENMASK(8, 2)
sys/dev/ic/qwzreg.h
10933
#define RX_MPDU_START_INFO4_MPDU_FRAG_NUMBER GENMASK(13, 10)
sys/dev/ic/qwzreg.h
10939
#define RX_MPDU_START_INFO4_MPDU_SEQ_NUM GENMASK(31, 20)
sys/dev/ic/qwzreg.h
10941
#define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10944
#define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10)
sys/dev/ic/qwzreg.h
10949
#define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16)
sys/dev/ic/qwzreg.h
10954
#define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0)
sys/dev/ic/qwzreg.h
10973
#define RX_MPDU_START_INFO7_VDEV_ID GENMASK(7, 0)
sys/dev/ic/qwzreg.h
10974
#define RX_MPDU_START_INFO7_SERVICE_CODE GENMASK(16, 8)
sys/dev/ic/qwzreg.h
10976
#define RX_MPDU_START_INFO7_SRC_INFO GENMASK(29, 18)
sys/dev/ic/qwzreg.h
11527
#define RX_MSDU_END_64_TLV_SRC_LINK_ID GENMASK(24, 22)
sys/dev/ic/qwzreg.h
11529
#define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
sys/dev/ic/qwzreg.h
11530
#define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)
sys/dev/ic/qwzreg.h
11532
#define RX_MSDU_END_INFO1_REPORTED_MPDU_LENGTH GENMASK(13, 0)
sys/dev/ic/qwzreg.h
11534
#define RX_MSDU_END_INFO2_CCE_SUPER_RULE GENMASK(13, 8)
sys/dev/ic/qwzreg.h
11538
#define RX_MSDU_END_INFO3_DA_OFFSET GENMASK(5, 0)
sys/dev/ic/qwzreg.h
11539
#define RX_MSDU_END_INFO3_SA_OFFSET GENMASK(11, 6)
sys/dev/ic/qwzreg.h
11543
#define RX_MSDU_END_INFO4_TCP_FLAG GENMASK(8, 0)
sys/dev/ic/qwzreg.h
11549
#define RX_MSDU_END_INFO5_TID GENMASK(6, 3)
sys/dev/ic/qwzreg.h
11553
#define RX_MSDU_END_INFO5_L3_HDR_PADDING GENMASK(11, 10)
sys/dev/ic/qwzreg.h
11560
#define RX_MSDU_END_INFO6_REO_DEST_IND GENMASK(5, 1)
sys/dev/ic/qwzreg.h
11561
#define RX_MSDU_END_INFO6_FLOW_IDX GENMASK(25, 6)
sys/dev/ic/qwzreg.h
11563
#define RX_MSDU_END_INFO6_MESH_STA GENMASK(28, 27)
sys/dev/ic/qwzreg.h
11568
#define RX_MSDU_END_INFO7_AGGR_COUNT GENMASK(7, 0)
sys/dev/ic/qwzreg.h
11579
#define RX_MSDU_END_INFO8_KEY_ID GENMASK(7, 0)
sys/dev/ic/qwzreg.h
11581
#define RX_MSDU_END_INFO9_SERVICE_CODE GENMASK(14, 6)
sys/dev/ic/qwzreg.h
11584
#define RX_MSDU_END_INFO9_DEST_CHIP_ID GENMASK(18, 17)
sys/dev/ic/qwzreg.h
11590
#define RX_MSDU_END_INFO10_MSDU_LENGTH GENMASK(13, 0)
sys/dev/ic/qwzreg.h
11593
#define RX_MSDU_END_INFO10_L3_OFFSET GENMASK(22, 16)
sys/dev/ic/qwzreg.h
11595
#define RX_MSDU_END_INFO10_L4_OFFSET GENMASK(31, 24)
sys/dev/ic/qwzreg.h
11597
#define RX_MSDU_END_INFO11_MSDU_NUMBER GENMASK(7, 0)
sys/dev/ic/qwzreg.h
11598
#define RX_MSDU_END_INFO11_DECAP_FORMAT GENMASK(9, 8)
sys/dev/ic/qwzreg.h
11606
#define RX_MSDU_END_INFO11_SEL_TOEPLITZ_HASH GENMASK(18, 17)
sys/dev/ic/qwzreg.h
11612
#define RX_MSDU_END_INFO11_IP4_IP6_NXT_HDR GENMASK(31, 24)
sys/dev/ic/qwzreg.h
11614
#define RX_MSDU_END_INFO12_USER_RSSI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
11615
#define RX_MSDU_END_INFO12_PKT_TYPE GENMASK(11, 8)
sys/dev/ic/qwzreg.h
11616
#define RX_MSDU_END_INFO12_SGI GENMASK(13, 12)
sys/dev/ic/qwzreg.h
11617
#define RX_MSDU_END_INFO12_RATE_MCS GENMASK(17, 14)
sys/dev/ic/qwzreg.h
11618
#define RX_MSDU_END_INFO12_RECV_BW GENMASK(20, 18)
sys/dev/ic/qwzreg.h
11619
#define RX_MSDU_END_INFO12_RECEPTION_TYPE GENMASK(23, 21)
sys/dev/ic/qwzreg.h
11621
#define RX_MSDU_END_INFO12_MIMO_SS_BITMAP GENMASK(30, 24)
sys/dev/ic/qwzreg.h
11656
#define RX_MSDU_END_INFO14_DECRYPT_STATUS_CODE GENMASK(12, 10)
sys/dev/ic/qwzreg.h
122
#define WMI_TLV_LEN GENMASK(15, 0)
sys/dev/ic/qwzreg.h
123
#define WMI_TLV_TAG GENMASK(31, 16)
sys/dev/ic/qwzreg.h
12416
#define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
sys/dev/ic/qwzreg.h
12417
#define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
sys/dev/ic/qwzreg.h
12421
#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
sys/dev/ic/qwzreg.h
12428
#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9)
sys/dev/ic/qwzreg.h
12429
#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
sys/dev/ic/qwzreg.h
12430
#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
sys/dev/ic/qwzreg.h
12432
#define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24)
sys/dev/ic/qwzreg.h
12433
#define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0)
sys/dev/ic/qwzreg.h
12452
#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
sys/dev/ic/qwzreg.h
126
#define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
sys/dev/ic/qwzreg.h
12602
#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwzreg.h
12603
#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
sys/dev/ic/qwzreg.h
12604
#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
sys/dev/ic/qwzreg.h
12605
#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
sys/dev/ic/qwzreg.h
12607
#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
sys/dev/ic/qwzreg.h
12608
#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
sys/dev/ic/qwzreg.h
12614
#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
sys/dev/ic/qwzreg.h
12616
#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
sys/dev/ic/qwzreg.h
12618
#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
sys/dev/ic/qwzreg.h
12675
#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwzreg.h
12677
#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9)
sys/dev/ic/qwzreg.h
12678
#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
sys/dev/ic/qwzreg.h
12787
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwzreg.h
12788
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
sys/dev/ic/qwzreg.h
12789
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
sys/dev/ic/qwzreg.h
12793
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
sys/dev/ic/qwzreg.h
13115
#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwzreg.h
13116
#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
sys/dev/ic/qwzreg.h
13121
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3)
sys/dev/ic/qwzreg.h
13159
#define HTT_T2H_MSG_TYPE GENMASK(7, 0)
sys/dev/ic/qwzreg.h
13160
#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
sys/dev/ic/qwzreg.h
13161
#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
sys/dev/ic/qwzreg.h
13167
#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
sys/dev/ic/qwzreg.h
13168
#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
sys/dev/ic/qwzreg.h
13169
#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
sys/dev/ic/qwzreg.h
13170
#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
sys/dev/ic/qwzreg.h
13171
#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
sys/dev/ic/qwzreg.h
13203
#define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
sys/dev/ic/qwzreg.h
13204
#define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
sys/dev/ic/qwzreg.h
13205
#define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
sys/dev/ic/qwzreg.h
13207
#define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
sys/dev/ic/qwzreg.h
13208
#define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
sys/dev/ic/qwzreg.h
13294
#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
sys/dev/ic/qwzreg.h
13295
#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
sys/dev/ic/qwzreg.h
13310
#define HTT_TLV_TAG GENMASK(11, 0)
sys/dev/ic/qwzreg.h
13311
#define HTT_TLV_LEN GENMASK(23, 12)
sys/dev/ic/qwzreg.h
13323
#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
sys/dev/ic/qwzreg.h
13324
#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
sys/dev/ic/qwzreg.h
13326
#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
sys/dev/ic/qwzreg.h
13353
#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
sys/dev/ic/qwzreg.h
13354
#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
sys/dev/ic/qwzreg.h
13357
#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
sys/dev/ic/qwzreg.h
13359
#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
sys/dev/ic/qwzreg.h
13362
#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
sys/dev/ic/qwzreg.h
13363
#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
sys/dev/ic/qwzreg.h
13364
#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
sys/dev/ic/qwzreg.h
13365
#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
sys/dev/ic/qwzreg.h
13366
#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
sys/dev/ic/qwzreg.h
13367
#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
sys/dev/ic/qwzreg.h
13384
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
sys/dev/ic/qwzreg.h
13387
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
sys/dev/ic/qwzreg.h
13388
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
sys/dev/ic/qwzreg.h
13389
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
sys/dev/ic/qwzreg.h
13390
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
sys/dev/ic/qwzreg.h
13391
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
sys/dev/ic/qwzreg.h
13392
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
sys/dev/ic/qwzreg.h
13411
#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
sys/dev/ic/qwzreg.h
13413
#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
sys/dev/ic/qwzreg.h
13414
#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
sys/dev/ic/qwzreg.h
13416
#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
sys/dev/ic/qwzreg.h
13447
#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
sys/dev/ic/qwzreg.h
13448
#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
sys/dev/ic/qwzreg.h
13450
#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
sys/dev/ic/qwzreg.h
13470
#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
sys/dev/ic/qwzreg.h
13471
#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
sys/dev/ic/qwzreg.h
13472
#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
sys/dev/ic/qwzreg.h
13770
#define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
sys/dev/ic/qwzreg.h
13779
#define HTT_MAC_ADDR_L32_0 GENMASK(7, 0)
sys/dev/ic/qwzreg.h
13780
#define HTT_MAC_ADDR_L32_1 GENMASK(15, 8)
sys/dev/ic/qwzreg.h
13781
#define HTT_MAC_ADDR_L32_2 GENMASK(23, 16)
sys/dev/ic/qwzreg.h
13782
#define HTT_MAC_ADDR_L32_3 GENMASK(31, 24)
sys/dev/ic/qwzreg.h
13783
#define HTT_MAC_ADDR_H16_0 GENMASK(7, 0)
sys/dev/ic/qwzreg.h
13784
#define HTT_MAC_ADDR_H16_1 GENMASK(15, 8)
sys/dev/ic/qwzreg.h
2628
#define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1)
sys/dev/ic/qwzreg.h
3418
#define WMI_SCAN_DWELL_MODE_MASK GENMASK(23, 21)
sys/dev/ic/qwzreg.h
3600
#define WMI_CHAN_INFO_MODE GENMASK(5, 0)
sys/dev/ic/qwzreg.h
3615
#define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0)
sys/dev/ic/qwzreg.h
3616
#define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8)
sys/dev/ic/qwzreg.h
3617
#define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16)
sys/dev/ic/qwzreg.h
3618
#define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24)
sys/dev/ic/qwzreg.h
3620
#define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0)
sys/dev/ic/qwzreg.h
3621
#define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8)
sys/dev/ic/qwzreg.h
3916
#define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0)
sys/dev/ic/qwzreg.h
3917
#define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8)
sys/dev/ic/qwzreg.h
3918
#define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20)
sys/dev/ic/qwzreg.h
3919
#define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
3921
#define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0)
sys/dev/ic/qwzreg.h
3922
#define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8)
sys/dev/ic/qwzreg.h
3923
#define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15)
sys/dev/ic/qwzreg.h
3925
#define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21)
sys/dev/ic/qwzreg.h
5726
#define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0)
sys/dev/ic/qwzreg.h
5727
#define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16)
sys/dev/ic/qwzreg.h
5729
#define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7529
#define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7530
#define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8)
sys/dev/ic/qwzreg.h
7531
#define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13)
sys/dev/ic/qwzreg.h
7545
#define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
sys/dev/ic/qwzreg.h
7546
#define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7547
#define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7554
#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16)
sys/dev/ic/qwzreg.h
7555
#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
sys/dev/ic/qwzreg.h
7556
#define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)
sys/dev/ic/qwzreg.h
7558
#define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7560
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)
sys/dev/ic/qwzreg.h
7561
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)
sys/dev/ic/qwzreg.h
7562
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)
sys/dev/ic/qwzreg.h
7563
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6)
sys/dev/ic/qwzreg.h
7564
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9)
sys/dev/ic/qwzreg.h
7565
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12)
sys/dev/ic/qwzreg.h
7566
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15)
sys/dev/ic/qwzreg.h
7567
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18)
sys/dev/ic/qwzreg.h
7568
#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21)
sys/dev/ic/qwzreg.h
7571
#define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
sys/dev/ic/qwzreg.h
7572
#define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7573
#define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8)
sys/dev/ic/qwzreg.h
7574
#define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7579
#define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16)
sys/dev/ic/qwzreg.h
7580
#define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
sys/dev/ic/qwzreg.h
7582
#define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7583
#define HAL_REO1_MISC_CTL_FRAG_DST_RING GENMASK(20, 17)
sys/dev/ic/qwzreg.h
7584
#define HAL_REO1_MISC_CTL_BAR_DST_RING GENMASK(24, 21)
sys/dev/ic/qwzreg.h
7587
#define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7588
#define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8)
sys/dev/ic/qwzreg.h
7589
#define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13)
sys/dev/ic/qwzreg.h
7595
#define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
sys/dev/ic/qwzreg.h
7603
#define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2)
sys/dev/ic/qwzreg.h
7604
#define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)
sys/dev/ic/qwzreg.h
7605
#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7606
#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8)
sys/dev/ic/qwzreg.h
7608
#define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8)
sys/dev/ic/qwzreg.h
7609
#define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8)
sys/dev/ic/qwzreg.h
7636
#define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
sys/dev/ic/qwzreg.h
7638
#define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
sys/dev/ic/qwzreg.h
7639
#define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)
sys/dev/ic/qwzreg.h
7640
#define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)
sys/dev/ic/qwzreg.h
8101
#define HAL_TLV_HDR_TAG GENMASK(9, 1)
sys/dev/ic/qwzreg.h
8102
#define HAL_TLV_HDR_LEN GENMASK(25, 10)
sys/dev/ic/qwzreg.h
8103
#define HAL_TLV_USR_ID GENMASK(31, 26)
sys/dev/ic/qwzreg.h
8112
#define HAL_TLV_64_HDR_TAG GENMASK(9, 1)
sys/dev/ic/qwzreg.h
8113
#define HAL_TLV_64_HDR_LEN GENMASK(21, 10)
sys/dev/ic/qwzreg.h
8210
#define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3)
sys/dev/ic/qwzreg.h
8211
#define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17)
sys/dev/ic/qwzreg.h
8394
#define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
8396
#define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9)
sys/dev/ic/qwzreg.h
8397
#define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11)
sys/dev/ic/qwzreg.h
8398
#define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16)
sys/dev/ic/qwzreg.h
8401
#define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1)
sys/dev/ic/qwzreg.h
8402
#define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5)
sys/dev/ic/qwzreg.h
8404
#define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
8405
#define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
8583
#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
8584
#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8)
sys/dev/ic/qwzreg.h
8585
#define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22)
sys/dev/ic/qwzreg.h
8588
#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)
sys/dev/ic/qwzreg.h
8589
#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2)
sys/dev/ic/qwzreg.h
8658
#define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)
sys/dev/ic/qwzreg.h
8659
#define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2)
sys/dev/ic/qwzreg.h
8660
#define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7)
sys/dev/ic/qwzreg.h
8662
#define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12)
sys/dev/ic/qwzreg.h
8665
#define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)
sys/dev/ic/qwzreg.h
8666
#define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
8667
#define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
8677
#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)
sys/dev/ic/qwzreg.h
8724
#define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17)
sys/dev/ic/qwzreg.h
8727
#define HAL_REO_CMD_UPD1_AC GENMASK(22, 21)
sys/dev/ic/qwzreg.h
8740
#define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11)
sys/dev/ic/qwzreg.h
8744
#define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8)
sys/dev/ic/qwzreg.h
8763
#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
8805
#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
8807
#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9)
sys/dev/ic/qwzreg.h
8816
#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
8819
#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10)
sys/dev/ic/qwzreg.h
8833
#define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2)
sys/dev/ic/qwzreg.h
8834
#define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4)
sys/dev/ic/qwzreg.h
8837
#define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12)
sys/dev/ic/qwzreg.h
8838
#define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14)
sys/dev/ic/qwzreg.h
8839
#define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16)
sys/dev/ic/qwzreg.h
8841
#define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0)
sys/dev/ic/qwzreg.h
8848
#define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23)
sys/dev/ic/qwzreg.h
8850
#define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0)
sys/dev/ic/qwzreg.h
8854
#define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22)
sys/dev/ic/qwzreg.h
8855
#define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26)
sys/dev/ic/qwzreg.h
8857
#define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0)
sys/dev/ic/qwzreg.h
8858
#define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6)
sys/dev/ic/qwzreg.h
8859
#define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26)
sys/dev/ic/qwzreg.h
8860
#define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30)
sys/dev/ic/qwzreg.h
8862
#define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
8863
#define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
9097
#define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
9098
#define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8)
sys/dev/ic/qwzreg.h
9103
#define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
9104
#define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
9145
#define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0)
sys/dev/ic/qwzreg.h
9147
#define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5)
sys/dev/ic/qwzreg.h
9148
#define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8)
sys/dev/ic/qwzreg.h
9150
#define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0)
sys/dev/ic/qwzreg.h
9152
#define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
9153
#define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
9188
#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
9193
#define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16)
sys/dev/ic/qwzreg.h
9195
#define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)
sys/dev/ic/qwzreg.h
9197
#define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
9285
#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
9286
#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
9338
#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16)
sys/dev/ic/qwzreg.h
9340
#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)
sys/dev/ic/qwzreg.h
9341
#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
9417
#define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1)
sys/dev/ic/qwzreg.h
9418
#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3)
sys/dev/ic/qwzreg.h
9421
#define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9)
sys/dev/ic/qwzreg.h
9422
#define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11)
sys/dev/ic/qwzreg.h
9424
#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16)
sys/dev/ic/qwzreg.h
9525
#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)
sys/dev/ic/qwzreg.h
9526
#define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3)
sys/dev/ic/qwzreg.h
9527
#define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6)
sys/dev/ic/qwzreg.h
9528
#define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)
sys/dev/ic/qwzreg.h
9529
#define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13)
sys/dev/ic/qwzreg.h
9530
#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
sys/dev/ic/qwzreg.h
9531
#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
sys/dev/ic/qwzreg.h
9532
#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24)
sys/dev/ic/qwzreg.h
9533
#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26)
sys/dev/ic/qwzreg.h
9536
#define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
sys/dev/ic/qwzreg.h
9537
#define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24)
sys/dev/ic/qwzreg.h
9539
#define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
9545
#define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)
sys/dev/ic/qwzreg.h
9547
#define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0)
sys/dev/ic/qwzreg.h
9548
#define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16)
sys/dev/ic/qwzreg.h
9549
#define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20)
sys/dev/ic/qwzreg.h
9550
#define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28)
sys/dev/ic/qwzreg.h
9552
#define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9)
sys/dev/ic/qwzreg.h
9553
#define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13)
sys/dev/ic/qwzreg.h
9779
#define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
sys/dev/ic/qwzreg.h
9780
#define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4)
sys/dev/ic/qwzreg.h
9781
#define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8)
sys/dev/ic/qwzreg.h
9796
#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)
sys/dev/ic/qwzreg.h
9830
#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)
sys/dev/ic/qwzreg.h
9833
#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1)
sys/dev/ic/qwzreg.h
9836
#define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5)
sys/dev/ic/qwzreg.h
9841
#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11)
sys/dev/ic/qwzreg.h
9846
#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23)
sys/dev/ic/qwzreg.h
9850
#define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1)
sys/dev/ic/qwzreg.h
9851
#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13)
sys/dev/ic/qwzreg.h
9856
#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)
sys/dev/ic/qwzreg.h
9859
#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4)
sys/dev/ic/qwzreg.h
9860
#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10)
sys/dev/ic/qwzreg.h
9861
#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16)
sys/dev/ic/qwzreg.h
9863
#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)
sys/dev/ic/qwzreg.h
9864
#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24)
sys/dev/ic/qwzreg.h
9866
#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)
sys/dev/ic/qwzreg.h
9867
#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12)
sys/dev/ic/qwzreg.h
9868
#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16)
sys/dev/ic/qwzreg.h
9958
#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
sys/dev/ic/qwzreg.h
9983
#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)
sys/dev/ic/qwzreg.h
9985
#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17)
sys/dev/ic/qwzreg.h
9988
#define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21)
sys/dev/ic/qwzreg.h
9999
#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0)
sys/dev/ic/qwzvar.h
1008
#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
sys/dev/ic/qwzvar.h
1009
#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
sys/dev/ic/qwzvar.h
1014
#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
sys/dev/ic/qwzvar.h
1015
#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
sys/dev/ic/qwzvar.h
1016
#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
sys/dev/ic/qwzvar.h
1065
#define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)
sys/dev/ic/qwzvar.h
1066
#define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
sys/dev/ic/qwzvar.h
1068
#define DP_REO_QREF_NUM GENMASK(31, 16)
sys/dev/ic/qwzvar.h
1206
#define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)
sys/dev/ic/qwzvar.h
513
#define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
sys/dev/ic/qwzvar.h
514
#define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
153
#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM - 1, 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1048
uint32_t xcc_mask = GENMASK(num_xcc - 1, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
450
mask = GENMASK(num_xcc - 1, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
453
mask = GENMASK(adev->sdma.num_instances - 1, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
457
mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
35
(num_inst ? GENMASK(num_inst - 1, 0) << (xcp_id * num_inst) : 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
832
xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
868
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
896
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
441
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
482
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
540
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
589
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
70
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
1424
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
1039
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
821
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1559
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1577
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2016
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2489
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2514
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2567
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
662
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
511
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2042
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1667
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3535
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3555
instlo &= GENMASK(31, 1);
sys/dev/pci/drm/apple/afk.c
19
#define RBEP_TYPE GENMASK(63, 48)
sys/dev/pci/drm/apple/afk.c
38
#define GETBUF_SIZE GENMASK(31, 16)
sys/dev/pci/drm/apple/afk.c
39
#define GETBUF_TAG GENMASK(15, 0)
sys/dev/pci/drm/apple/afk.c
40
#define GETBUF_ACK_DVA GENMASK(47, 0)
sys/dev/pci/drm/apple/afk.c
42
#define INITRB_OFFSET GENMASK(47, 32)
sys/dev/pci/drm/apple/afk.c
43
#define INITRB_SIZE GENMASK(31, 16)
sys/dev/pci/drm/apple/afk.c
44
#define INITRB_TAG GENMASK(15, 0)
sys/dev/pci/drm/apple/afk.c
46
#define SEND_WPTR GENMASK(31, 0)
sys/dev/pci/drm/apple/dptxep.h
35
#define DCPDPTX_REMOTE_PORT_CORE GENMASK(3, 0)
sys/dev/pci/drm/apple/dptxep.h
36
#define DCPDPTX_REMOTE_PORT_ATC GENMASK(7, 4)
sys/dev/pci/drm/apple/dptxep.h
37
#define DCPDPTX_REMOTE_PORT_DIE GENMASK(11, 8)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1030
reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
454
buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
456
buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
594
req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0),
sys/dev/pci/drm/display/drm_dp_mst_topology.c
598
req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3),
sys/dev/pci/drm/drm_client_modeset.c
654
mask = GENMASK(count - 1, 0);
sys/dev/pci/drm/drm_displayid_internal.h
145
#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
sys/dev/pci/drm/drm_displayid_internal.h
146
#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
sys/dev/pci/drm/drm_format_internal.h
108
return GENMASK(31, 24) | /* fill alpha bits */
sys/dev/pci/drm/drm_format_internal.h
130
return GENMASK(31, 24) | /* fill alpha bits */
sys/dev/pci/drm/drm_format_internal.h
144
return GENMASK(31, 30) | /* set alpha bits */
sys/dev/pci/drm/drm_format_internal.h
158
return GENMASK(31, 30) | /* set alpha bits */
sys/dev/pci/drm/drm_format_internal.h
96
return pix & GENMASK(23, 0);
sys/dev/pci/drm/i915/display/intel_bw.c
177
qgv_points = GENMASK(num_qgv_points - 1, 0);
sys/dev/pci/drm/i915/display/intel_bw.c
180
psf_points = GENMASK(num_psf_gv_points - 1, 0);
sys/dev/pci/drm/i915/display/intel_display.c
3551
primary_pipes &= GENMASK(pipe, 0);
sys/dev/pci/drm/i915/display/intel_display_device.c
1123
.abox_mask = GENMASK(1, 0), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1301
.abox_mask = GENMASK(1, 0), \
sys/dev/pci/drm/i915/display/intel_display_device.c
961
.abox_mask = GENMASK(2, 1), \
sys/dev/pci/drm/i915/display/intel_dp.c
2680
pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
86
# define INTEL_EDP_TCON_USAGE_MASK GENMASK(0, 3)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
94
# define INTEL_EDP_TCON_OPTIMIZATION_STRENGTH_MASK GENMASK(5, 7)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
662
pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
sys/dev/pci/drm/i915/display/intel_frontbuffer.h
68
GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
sys/dev/pci/drm/i915/display/intel_vbt_defs.h
454
#define BDB_263_VBT_EDP_RATES_MASK GENMASK(BDB_263_VBT_EDP_NUM_RATES - 1, 0)
sys/dev/pci/drm/i915/gt/intel_engine.h
88
((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
900
info->engine_mask &= ~GENMASK(CCS3, CCS0);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
968
GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
160
#define GEN12_CSB_SW_CTX_ID_MASK GENMASK(25, 15)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
166
#define XEHP_CSB_SW_CTX_ID_MASK GENMASK(31, 10)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2465
if (engine->execlists.error_interrupt & GENMASK(15, 0))
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2495
eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
3589
engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
232
#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
244
#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1596
#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1597
#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
sys/dev/pci/drm/i915/gt/intel_lrc.h
90
#define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
sys/dev/pci/drm/i915/gt/intel_lrc.h
97
#define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9)
sys/dev/pci/drm/i915/gt/intel_sseu.c
153
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
sys/dev/pci/drm/i915/gt/intel_sseu.c
496
subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1022
if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1182
if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1335
if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {
sys/dev/pci/drm/i915/gt/selftest_lrc.c
209
if ((lri & GENMASK(31, 23)) != LRI_HEADER) {
sys/dev/pci/drm/i915/gt/selftest_lrc.c
32
#define LRI_LENGTH_MASK GENMASK(7, 0)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
115
#define CAP_HDR_CAPTURE_VFID GENMASK(7, 0)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
117
#define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
118
#define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
119
#define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
123
#define CAP_HDR_NUM_MMIOS GENMASK(9, 0)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
139
#define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
141
#define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
142
#define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
71
#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h
102
#define INTEL_GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h
72
#define INTEL_GSC_BPDT_ENTRY_TYPE_MASK GENMASK(15, 0)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c
60
#define GSC_PROXY_TYPE GENMASK(7, 0)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c
61
#define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
378
#define GUC_REGSET_STEERING_GROUP GENMASK(15, 12)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
379
#define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
67
#define WQ_TYPE_MASK GENMASK(7, 0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
68
#define WQ_LEN_MASK GENMASK(26, 16)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
70
#define WQ_GUC_ID_MASK GENMASK(15, 0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
71
#define WQ_RING_TAIL_MASK GENMASK(28, 18)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1037
(cmd_val(s, i) & GENMASK(22, 2))
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1040
(cmd_val(s, i) & GENMASK(22, 18))
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1043
(cmd_val(s, i) & GENMASK(31, 2))
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1046
(cmd_val(s, i) & GENMASK(15, 0))
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1205
gma = cmd_val(s, 2) & GENMASK(31, 3);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1307
v = (dword0 & GENMASK(21, 19)) >> 19;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1314
info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1316
info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1317
info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1343
u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1382
info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1383
info->tile_val = (dword1 & GENMASK(2, 0));
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1384
info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1385
info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1403
stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1405
GENMASK(12, 10)) >> 10;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1408
GENMASK(15, 6)) >> 6;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1429
set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1432
set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1434
set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1437
set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1439
set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1628
gma = cmd_val(s, 2) & GENMASK(31, 2);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1631
gma_low = cmd_val(s, 1) & GENMASK(31, 2);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1632
gma_high = cmd_val(s, 2) & GENMASK(15, 0);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1667
int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1684
gma = cmd_val(s, 1) & GENMASK(31, 2);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1686
gma_high = cmd_val(s, 2) & GENMASK(15, 0);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1734
gma = cmd_val(s, 1) & GENMASK(31, 3);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1736
gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
396
FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
sys/dev/pci/drm/i915/gvt/gvt.h
486
*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
sys/dev/pci/drm/i915/gvt/handlers.c
171
offset &= ~GENMASK(11, 0);
sys/dev/pci/drm/i915/gvt/handlers.c
287
(((new) & GENMASK(31, 16)) \
sys/dev/pci/drm/i915/gvt/handlers.c
288
| ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
sys/dev/pci/drm/i915/gvt/handlers.c
321
vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
sys/dev/pci/drm/i915/gvt/handlers.c
970
data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
sys/dev/pci/drm/i915/gvt/handlers.c
985
sticky_mask = GENMASK(27, 26) | (1 << 24);
sys/dev/pci/drm/i915/gvt/interrupt.c
439
if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))
sys/dev/pci/drm/i915/i915_cmd_parser.c
500
#define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)
sys/dev/pci/drm/i915/i915_params.h
35
#define ENABLE_GUC_MASK GENMASK(1, 0)
sys/dev/pci/drm/i915/intel_wakeref.h
139
#define INTEL_WAKEREF_PUT_DELAY_MASK GENMASK(BITS_PER_LONG - 1, 1)
sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h
47
#define PXP43_INIT_SESSION_APPID GENMASK(17, 2)
sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
34
#define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)
sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
35
#define PXP_CMDHDR_EXTDATA_APP_TYPE GENMASK(1, 1)
sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
36
#define PXP_CMDHDR_EXTDATA_SESSION_ID GENMASK(17, 2)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1200
# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1201
# define DP_ADAPTIVE_SYNC_SDP_LENGTH GENMASK(5, 0)
sys/dev/pci/drm/include/linux/bits.h
106
((u16)(GENMASK(__high, __low) + \
sys/dev/pci/drm/include/linux/bits.h
46
((u32)(GENMASK(__high, __low) + \
sys/dev/pci/drm/include/linux/bits.h
76
((u8)(GENMASK(__high, __low) + \
sys/dev/pci/if_mwx.c
4450
i &= GENMASK(3, 0);
sys/dev/pci/if_mwxreg.h
108
#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
sys/dev/pci/if_mwxreg.h
673
#define MT_TXD3_SEQ GENMASK(27, 16)
sys/dev/pci/if_mwxreg.h
676
#define MT_TXD3_TX_COUNT GENMASK(10, 6)
sys/dev/pci/if_mwxreg.h
715
#define MT_TXD7_PSE_FID GENMASK(27, 16)
sys/dev/pci/if_mwxreg.h
716
#define MT_TXD7_SPE_IDX GENMASK(15, 11)
sys/dev/pci/if_mwxreg.h
811
#define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
sys/dev/pci/if_mwxreg.h
813
#define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
sys/dev/pci/if_mwxreg.h
814
#define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
sys/dev/pci/if_mwxreg.h
816
#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
sys/dev/pci/if_mwxreg.h
97
#define MT_WTBL_LMAC_ID GENMASK(14, 8)
sys/dev/pci/if_mwxreg.h
98
#define MT_WTBL_LMAC_DW GENMASK(7, 2)
sys/dev/pci/if_qwx_pci.c
116
#define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
sys/dev/pci/if_qwx_pci.c
118
#define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
sys/dev/pci/if_qwx_pci.c
124
#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
sys/dev/pci/if_qwx_pci.c
125
#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
sys/dev/pci/if_qwx_pci.c
183
#define MHI_CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
sys/dev/pci/if_qwx_pci.c
190
#define MHI_CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
sys/dev/pci/if_qwx_pci.c
194
#define MHI_CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
sys/dev/pci/if_qwx_pci.c
195
#define MHI_CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
sys/dev/pci/if_qwx_pci.c
206
#define MHI_EV_CTX_RESERVED_MASK GENMASK(7, 0)
sys/dev/pci/if_qwx_pci.c
207
#define MHI_EV_CTX_INTMODC_MASK GENMASK(15, 8)
sys/dev/pci/if_qwx_pci.c
208
#define MHI_EV_CTX_INTMODT_MASK GENMASK(31, 16)
sys/dev/pci/if_qwx_pci.c
2242
#define MHI_CFG_NHWER_MASK GENMASK(31, 24)
sys/dev/pci/if_qwx_pci.c
2244
#define MHI_CFG_NER_MASK GENMASK(23, 16)
sys/dev/pci/if_qwx_pci.c
2246
#define MHI_CFG_NHWCH_MASK GENMASK(15, 8)
sys/dev/pci/if_qwx_pci.c
2248
#define MHI_CFG_NCH_MASK GENMASK(7, 0)
sys/dev/pci/if_qwx_pci.c
2272
#define MHI_CTRL_MHISTATE_MASK GENMASK(15, 8)
sys/dev/pci/if_qwx_pci.c
2275
#define MHI_STATUS_MHISTATE_MASK GENMASK(15, 8)
sys/dev/pci/if_qwx_pci.c
2320
#define MHI_BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwx_pci.c
2322
#define MHI_BHI_STATUS_MASK GENMASK(31, 30)
sys/dev/pci/if_qwx_pci.c
2337
#define MHI_BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwx_pci.c
2339
#define MHI_BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwx_pci.c
2341
#define MHI_BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
sys/dev/pci/if_qwx_pci.c
2346
#define MHI_BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwx_pci.c
2348
#define MHI_BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwx_pci.c
2350
#define MHI_BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
sys/dev/pci/if_qwx_pci.c
2371
#define MHI_TRE_CMD_CHID_MASK GENMASK(31, 24)
sys/dev/pci/if_qwx_pci.c
2373
#define MHI_TRE_CMD_CMDID_MASK GENMASK(23, 16)
sys/dev/pci/if_qwx_pci.c
2376
#define MHI_TRE0_EV_LEN_MASK GENMASK(15, 0)
sys/dev/pci/if_qwx_pci.c
2378
#define MHI_TRE0_EV_CODE_MASK GENMASK(31, 24)
sys/dev/pci/if_qwx_pci.c
2380
#define MHI_TRE1_EV_TYPE_MASK GENMASK(23, 16)
sys/dev/pci/if_qwx_pci.c
2382
#define MHI_TRE1_EV_CHID_MASK GENMASK(31, 24)
sys/dev/pci/if_qwx_pci.c
2385
#define MHI_TRE0_DATA_LEN_MASK GENMASK(15, 0)
sys/dev/pci/if_qwx_pci.c
2391
#define MHI_TRE1_DATA_TYPE_MASK GENMASK(23, 16)
sys/dev/pci/if_qwz_pci.c
116
#define ATH12K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
sys/dev/pci/if_qwz_pci.c
118
#define ATH12K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
sys/dev/pci/if_qwz_pci.c
119
#define ATH12K_PCI_WINDOW_STATIC_MASK GENMASK(31, 6)
sys/dev/pci/if_qwz_pci.c
125
#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
sys/dev/pci/if_qwz_pci.c
126
#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
sys/dev/pci/if_qwz_pci.c
185
#define MHI_CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
sys/dev/pci/if_qwz_pci.c
192
#define MHI_CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
sys/dev/pci/if_qwz_pci.c
196
#define MHI_CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
sys/dev/pci/if_qwz_pci.c
197
#define MHI_CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
sys/dev/pci/if_qwz_pci.c
207
#define MHI_EV_CTX_RESERVED_MASK GENMASK(7, 0)
sys/dev/pci/if_qwz_pci.c
208
#define MHI_EV_CTX_INTMODC_MASK GENMASK(15, 8)
sys/dev/pci/if_qwz_pci.c
209
#define MHI_EV_CTX_INTMODT_MASK GENMASK(31, 16)
sys/dev/pci/if_qwz_pci.c
2109
#define MHI_CFG_NHWER_MASK GENMASK(31, 24)
sys/dev/pci/if_qwz_pci.c
2111
#define MHI_CFG_NER_MASK GENMASK(23, 16)
sys/dev/pci/if_qwz_pci.c
2113
#define MHI_CFG_NHWCH_MASK GENMASK(15, 8)
sys/dev/pci/if_qwz_pci.c
2115
#define MHI_CFG_NCH_MASK GENMASK(7, 0)
sys/dev/pci/if_qwz_pci.c
2139
#define MHI_CTRL_MHISTATE_MASK GENMASK(15, 8)
sys/dev/pci/if_qwz_pci.c
2142
#define MHI_STATUS_MHISTATE_MASK GENMASK(15, 8)
sys/dev/pci/if_qwz_pci.c
2187
#define MHI_BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwz_pci.c
2189
#define MHI_BHI_STATUS_MASK GENMASK(31, 30)
sys/dev/pci/if_qwz_pci.c
2204
#define MHI_BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwz_pci.c
2206
#define MHI_BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwz_pci.c
2208
#define MHI_BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
sys/dev/pci/if_qwz_pci.c
2213
#define MHI_BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwz_pci.c
2215
#define MHI_BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
sys/dev/pci/if_qwz_pci.c
2217
#define MHI_BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
sys/dev/pci/if_qwz_pci.c
2238
#define MHI_TRE_CMD_CHID_MASK GENMASK(31, 24)
sys/dev/pci/if_qwz_pci.c
2240
#define MHI_TRE_CMD_CMDID_MASK GENMASK(23, 16)
sys/dev/pci/if_qwz_pci.c
2243
#define MHI_TRE0_EV_LEN_MASK GENMASK(15, 0)
sys/dev/pci/if_qwz_pci.c
2245
#define MHI_TRE0_EV_CODE_MASK GENMASK(31, 24)
sys/dev/pci/if_qwz_pci.c
2247
#define MHI_TRE1_EV_TYPE_MASK GENMASK(23, 16)
sys/dev/pci/if_qwz_pci.c
2249
#define MHI_TRE1_EV_CHID_MASK GENMASK(31, 24)
sys/dev/pci/if_qwz_pci.c
2252
#define MHI_TRE0_DATA_LEN_MASK GENMASK(15, 0)
sys/dev/pci/if_qwz_pci.c
2258
#define MHI_TRE1_DATA_TYPE_MASK GENMASK(23, 16)
sys/sys/videoio.h
1863
#define V4L2_FWHT_FL_COMPONENTS_NUM_MSK GENMASK(18, 16)
sys/sys/videoio.h
1867
#define V4L2_FWHT_FL_PIXENC_MSK GENMASK(20, 19)