GEN8_RING_CS_GPR
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),
#define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x)
const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40);
MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40);
MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40);
MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40);
gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));