sys/dev/pci/drm/i915/gt/intel_lrc.c

1645

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1651

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1660

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1932

whitelist_mcr_reg(w, GEN8_L3SQCREG4);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1953

whitelist_mcr_reg(w, GEN8_L3SQCREG4);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2366

GEN8_L3SQCREG4,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2495

GEN8_L3SQCREG4,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2501

wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

926

if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||

sys/dev/pci/drm/i915/gvt/handlers.c

2574

MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

845

MMIO_D(GEN8_L3SQCREG4);