sys/dev/pci/drm/i915/gt/intel_workarounds.c

1526

wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1569

wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1602

wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

45

intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0,

sys/dev/pci/drm/i915/i915_irq.c

171

misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,

sys/dev/pci/drm/i915/i915_irq.c

173

intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);

sys/dev/pci/drm/i915/i915_irq.c

215

intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);

sys/dev/pci/drm/i915/i915_perf.c

2418

intel_uncore_rmw(uncore, GEN7_MISCCPCTL,

sys/dev/pci/drm/i915/i915_perf.c

2434

intel_uncore_rmw(uncore, GEN7_MISCCPCTL,

sys/dev/pci/drm/i915/intel_clock_gating.c

334

misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,

sys/dev/pci/drm/i915/intel_clock_gating.c

349

intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);

sys/dev/pci/drm/i915/intel_clock_gating.c

414

intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

817

MMIO_D(GEN7_MISCCPCTL);

sys/dev/pci/drm/i915/vlv_suspend.c

150

s->misccpctl = intel_uncore_read(uncore, GEN7_MISCCPCTL);

sys/dev/pci/drm/i915/vlv_suspend.c

235

intel_uncore_write(uncore, GEN7_MISCCPCTL, s->misccpctl);