sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

200

bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

386

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

390

lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

392

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

458

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

463

lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

466

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2033

AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2039

AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2044

AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

416

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

420

lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

422

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

504

UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

509

lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

512

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1483

AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1488

AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1493

AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

630

WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

634

lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

636

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

717

VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

722

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

725

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1477

AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1480

AMDGPU_VCN_STACK_SIZE;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

552

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

556

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

558

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

639

VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

644

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

647

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1432

AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1435

AMDGPU_VCN_STACK_SIZE;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

481

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

485

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

487

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

578

VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

583

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

586

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1080

regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1083

AMDGPU_VCN_STACK_SIZE;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

494

AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

499

AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

502

AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

600

VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

606

AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

610

AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

432

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

436

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

438

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

533

VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

538

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

542

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

396

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

400

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

402

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

494

VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

499

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

502

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

456

WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

460

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

462

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

556

VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

562

AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

566

AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

872

regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

875

AMDGPU_VCN_STACK_SIZE;